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| 1996 data sheet the mark shows major revised points. 16-bit single-chip microcontroller mos integrated circuit m pd784907, 784908 document no. u11680ej2v0ds00 (2nd edition) date published february 1999 n cp(k) printed in japan the m pd784907 and m pd784908 are products of the m pd784908 subseries in the 78k/iv series. these products contain various peripheral hardware such as iebus tm controller, rom, ram, i/o ports, 8-bit resolution a/d, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance cpu. in addition, the m pd78p4908 (one-time prom product), which is used to evaluate the functions of mask rom versions, and development tools are also available. detailed function descriptions are provided in the following user's manuals. be sure to read them before designing. m pd784908 subseries user's manual hardware : u11787e 78k/iv series user's manual instruction : u10905e features the information in this document is subject to change without notice. ? 78k/iv series ? minimum instruction execution time: 320 ns (at 6.29 mhz) 160 ns (at 12.58 mhz) ? number of i/o ports: 80 ? timer/counters: 16-bit timer/counter 3 units 16-bit timer 1 unit ? serial interface: 4 channels uart/ioe (3-wire serial i/o): 2 channels csi (3-wire serial i/o): 2 channels ? pwm outputs: 2 ? standby function halt/stop/idle mode ? clock frequency division function ? watchdog timer: 1 channel ? clock output function selectable from f clk , f clk /2, f clk /4, f clk /8, or f clk /16 ? a/d converter: 8-bit resolution 8 channels ? on-chip iebus controller ? watch timer ? low-power consumption ? supply voltage: v dd = 4.0 to 5.5 v (main clock: f xx = 12.58 mhz, internal system clock = f xx , f cyk = 79 ns) v dd = 3.5 to 5.5 v (other than above, f cyk = 159 ns) applications car audios, etc. this document describes the m pd784908 unless otherwise specified.
m pd784907, 784908 2 data sheet u11680ej2v0ds00 ordering information part number package internal rom internal ram (bytes) (bytes) m pd784907gf- -3ba 100-pin plastic qfp (14 20 mm) 96 k 3,584 m pd784908gf- -3ba 100-pin plastic qfp (14 20 mm) 128 k 4,352 remark indicates rom code suffix. m pd784907, 784908 3 data sheet u11680ej2v0ds00 78k/iv series product lineup pd784026 pd784038y i 2 c bus supported pd784038 enhanced internal memory capacity, pin compatible with the pd784026 pd784225y multi-master i 2 c bus supported pd784225 80 pins, rom correction added pd784218y multi-master i 2 c bus supported multi-master i 2 c bus supported pd784218 enhanced internal memory capacity, rom correction added pd784928y multi-master i 2 c bus supported pd784928 enhanced functions of the pd784915 pd784216y pd784054 pd784216 pd784046 pd784908 on-chip 10-bit a/d 100 pins, enhanced i/o and internal memory capacity enhanced a/d, 16-bit timer, and power management pd784915 for software servo control, on-chip analog circuit for vcr, enhanced timer on-chip iebus controller standard models assp models : under mass production : under development m m m m m m m m m m m m m pd784955 for dc inverter control m m m m m pd784938 enhanced functions of the pd784908, enhanced internal memory capacity, rom correction added m m m pd784907, 784908 4 data sheet u11680ej2v0ds00 functions part number m pd784907 m pd784908 item number of basic instructions 113 (mnemonics) general-purpose register 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution 320 ns/636 ns/1.27 m s/2.54 m s (at 6.29 mhz) time 160 ns/320 ns/636 ns/1.27 m s (at 12.58 mhz) internal rom 96 k 128 k memory ram 3,584 bytes 4,352 bytes memory space 1 mbyte with program and data spaces combined i/o ports total 80 input 8 input/output 72 additional led direct 24 function drive outputs pins note transistor 8 direct drive n-ch open 4 drain real-time output ports 4 bits 2, or 8 bits 1 iebus controller incorporated (simplified) timer/counter timer/counter 0: timer register 1 pulse output capability (16 bits) capture register 1 ? toggle output compare register 2 ? pwm/ppg output ? one-shot pulse output timer/counter 1: timer register 1 real-time output port (16 bits) capture register 1 capture/compare register 1 compare register 1 timer/counter 2: timer register 1 pulse output capability (16 bits) capture register 1 ? toggle output capture/compare register 1 ? pwm/ppg output compare register 1 timer 3: timer register 1 (16 bits) compare register 1 watch timer interrupt requests are generated at 0.5-second intervals. (a watch clock oscillator is incorporated.) either the main clock (6.29 mhz/12.58 mhz) or watch clock (32.7 khz) can be selected as the input clock. clock output selectable from f clk , f clk /2, f clk /4, f clk /8, or f clk /16 (can be used as a 1-bit output port) pwm outputs 12-bit resolution 2 channels serial interface uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) csi (3-wire serial i/o): 2 channels a/d converter 8-bit resolution 8 channels note additional function pins are included in the i/o pins. m pd784907, 784908 5 data sheet u11680ej2v0ds00 part number m pd784907 m pd784908 item watchdog timer 1 channel standby halt/stop/idle modes interrupt hardware source 27 (20 internal, 7 external (sampling clock variable input: 1)) software source brk or brkcs instruction, operand error non-maskable 1 internal, 1 external maskable 19 internal, 6 external 4-level programmable priority 3 operation statuses: vectored interrupt, macro service, context switching power supply voltage v dd = 4.0 to 5.5 v (main clock: f xx = 12.58 mhz, internal system clock = f xx , f cyk = 79 ns) v dd = 3.5 to 5.5 v (other than above, f cyk = 159 ns) package 100-pin plastic qfp (14 20 mm) m pd784907, 784908 6 data sheet u11680ej2v0ds00 contents 1. differences between m pd784908 subseries products ....................................... 8 2. major differences between m pd784908 and m pd78098 subseries .................. 9 3. pin configuration (top view) ......................................................................................... 10 4. system configuration example (automotive car audio (tuner deck)) ..... 12 5. block diagram ..................................................................................................................... 13 6. pin function ........................................................................................................................... 14 6.1 port pins ............................................................................................................................... ............. 14 6.2 non-port pins ............................................................................................................................... .... 16 6.3 pin i/o circuits and recommended connections of unused pins .......................................... 18 7. cpu architecture ............................................................................................................... 22 7.1 memory space ............................................................................................................................... ... 22 7.2 cpu registers ............................................................................................................................... ... 25 7.2.1 general-purpose registers ................................................................................................ 25 7.2.2 control registers ................................................................................................................ 26 7.2.3 special function registers (sfrs) .................................................................................... 27 8. peripheral hardware functions ................................................................................ 33 8.1 ports ............................................................................................................................... .................... 33 8.2 clock generator ............................................................................................................................... 35 8.3 real-time output port ..................................................................................................................... 38 8.4 timers/counters ............................................................................................................................... 39 8.5 watch timer ............................................................................................................................... ....... 41 8.6 pwm output (pwm0, pwm1) .......................................................................................................... 42 8.7 a/d converter ............................................................................................................................... .... 43 8.8 serial interface ............................................................................................................................... .. 44 8.8.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) ....................................... 45 8.8.2 clocked serial interface (csi) ........................................................................................... 47 8.9 clock output function .................................................................................................................... 48 8.10 edge detection function ................................................................................................................ 49 8.11 watchdog timer ............................................................................................................................... 49 8.12 simplified iebus controller ............................................................................................................ 50 9. interrupt function ............................................................................................................ 53 9.1 interrupt source ............................................................................................................................... 53 9.2 vectored interrupt ............................................................................................................................ 55 9.3 context switching ............................................................................................................................ 56 9.4 macro service ............................................................................................................................... .... 56 9.5 examples of macro service applications .................................................................................... 57 m pd784907, 784908 7 data sheet u11680ej2v0ds00 10. local bus interface ......................................................................................................... 59 10.1 memory expansion .......................................................................................................................... 59 10.2 memory space ............................................................................................................................... ... 60 10.3 programmable wait ......................................................................................................................... 61 10.4 pseudo-static ram refresh function .......................................................................................... 61 10.5 bus hold function ........................................................................................................................... 61 11. standby function ............................................................................................................... 62 12. reset function ..................................................................................................................... 63 13. regulator .............................................................................................................................. 6 4 14. instruction set .................................................................................................................... 65 15. electrical specifications .............................................................................................. 70 16. package drawing ................................................................................................................ 89 17. recommended soldering conditions ........................................................................ 90 appendix a development tools .......................................................................................... 91 appendix b related documents ......................................................................................... 94 m pd784907, 784908 8 data sheet u11680ej2v0ds00 1. differences between m pd784908 subseries products the only difference between the m pd784907 and m pd784908 is their internal memory capacities. the m pd78p4908 is produced by replacing the mask rom in the m pd784907 or m pd784908 with 128-kbyte one- time prom. table 1-1 shows the differences between these products. table 1-1. differences between the m pd784908 subseries products part number m pd784907 m pd784908 m pd78p4908 item internal rom 96 k (mask rom) 128 k (mask rom) 128 k (one-time prom) internal ram 3,584 bytes 4,352 bytes regulator provided none power supply voltage v dd = 4.0 to 5.5 v v dd = 4.5 to 5.5 v (main clock: f xx = 12.58 mhz, internal system clock = f xx , (main clock: f xx = 12.58 mhz, f cyk = 79 ns) internal system clock = f xx , v dd = 3.5 to 5.5 v f cyk = 79 ns) (other than above, f cyk = 159 ns) v dd = 4.0 to 5.5 v (other than above, f cyk = 159 ns) electrical specifications refer to the data sheet of each product. m pd784907, 784908 9 data sheet u11680ej2v0ds00 2. major differences between m pd784908 and m pd78098 subseries series name m pd784908 subseries m pd78098 subseries item number of basic instructions 113 63 (mnemonics) minimum instruction execution 320/160 ns 480 ns time (at 6.29/12.58 mhz operation) (at 6.29 mhz operation) timer/counter 16-bit timer/counter 1 16-bit timer/counter 1 8/16-bit timer/counter 2 8/16-bit timer/counter 2 8/16-bit timer 1 watch timer watch timer single clock dual clock watch clock for clock operation watchdog timer provided serial interface uart/ioe (3-wire serial i/o): 2 channels uart (3-wire serial i/o): 1 channel csi (3-wire serial i/o): 2 channels csi/sbi (3-wire serial i/o): 1 channel csi (3-wire serial i/o): 1 channel pwm output 2 none a/d converter 8-bit resolution 8 channels d/a converter none interrupt hardware source 27 23 (two test flags) internal 20 14 external 7 7 external extended function provided (up to 1 mbyte) none iebus controller incorporated (simplified) incorporated (complete hardware) power supply voltage ? mask rom version v dd = 2.7 to 6.0 v v dd = 4.0 to 5.5 v (main clock: f xx = 12.58 mhz, internal system clock = f xx , f cyk = 79 ns) v dd = 3.5 to 5.5 v (other than above, f cyk = 159 ns) ? prom version v dd = 4.5 to 5.5 v (main clock: f xx = 12.58 mhz, internal system clock = f xx , f cyk = 79 ns) v dd = 4.0 to 5.5 v (other than above, f cyk = 159 ns) package 100-pin plastic qfp (14 20 mm) 80-pin plastic qfp (14 14 mm) 80-pin plastic wqfn (14 14 mm): m pd78p098a only m pd784907, 784908 10 data sheet u11680ej2v0ds00 3. pin configuration (top view) ? 100-pin plastic qfp (14 20 mm) m pd784907gf- -3ba m pd784908gf- -3ba notes 1. connect the test pin directly to v ss . 2. connect the regoff pin directly to v ss (select regulator operation). 3. connect the regc pin to v ss via a capacitor of the order of 1 m f. p35/to1 100 p34/to0 99 p33/so0 98 p32/sck0 97 p31/txd/so1 96 p30/rxd/si1 95 p27/si0 94 p26/intp5 93 p25/intp4/asck/sck1 92 p24/intp3 91 p23/intp2/ci 90 p22/intp1 89 p21/intp0 88 p20/nmi 87 tx 86 rx 85 av ss 84 av ref1 83 av dd 82 p77/ani7 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 p76/ani6 1 p36/to2 2 p37/to3 3 p100 4 p101 5 p102 6 p103 7 p104 8 p105/sck3 9 p106/si3 10 p107/so3 11 reset 12 xt2 13 xt1 14 v ss 15 x2 16 x1 17 regoff note 2 18 regc note 3 19 v dd 20 p00 21 p01 22 p02 23 p03 24 p04 25 p05 26 p06 27 p07 28 p67/refrq/hldak 29 p66/wait/hldrq 30 p65/wr 79 p75/ani5 78 p74/ani4 77 p73/ani3 76 p72/ani2 75 p71/ani1 74 p70/ani0 73 test note 1 72 pwm1 71 pwm0 70 p17 69 p16 68 p15 67 p14/txd2/so2 66 p13/rxd2/si2 65 p12/asck2/sck2 64 p11 62 astb/clkout 63 p10 61 p90 60 p91 59 p92 58 p93 57 p94 56 p95 55 p96 54 p97 53 p40/ad0 52 p41/ad1 51 p42/ad2 p64/rd p63/a19 p62/a18 p61/a17 p60/a16 p57/a15 p56/a14 p55/a13 p54/a12 v ss v dd p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 m pd784907, 784908 11 data sheet u11680ej2v0ds00 a8 to a19: address bus ad0 to ad7: address/data bus ani0 to ani7: analog input asck, asck2: asynchronous serial clock astb: address strobe av dd : analog power supply av ref1 : reference voltage av ss : analog ground ci: clock input clkout: clock output hldak: hold acknowledge hldrq: hold request intp0 to intp5: interrupt from peripherals nmi: non-maskable interrupt p00 to p07: port 0 p10 to p17: port 1 p20 to p27: port 2 p30 to p37: port 3 p40 to p47: port 4 p50 to p57: port 5 p60 to p67: port 6 p70 to p77: port 7 p90 to p97: port 9 p100 to p107: port 10 pwm0, pwm1: pulse width modulation output rd: read strobe refrq: refresh request regc: regulator capacitance regoff: regulator off reset: reset rx: iebus receive data r x d, r x d2: receive data sck0 to sck3: serial clock si0 to si3: serial input so0 to so3: serial output test: test to0 to to3: timer output tx: iebus transmit data t x d, t x d2: transmit data v dd : power supply v ss : ground wait: wait wr: write strobe x1, x2: crystal (main system clock) xt1, xt2: crystal (watch) m pd784907, 784908 12 data sheet u11680ej2v0ds00 4. system configuration example (automotive car audio (tuner deck)) front panel pd784908 remote-controll signal reception circuit pc2800a, etc. m m m key matrix fip tm fip controller/driver pd16312, etc. led display audio control circuit electronic volume interrupt input 3-wire serial i/o sio with automatic transmission/reception function eeprom tm general-purpose port 3-wire serial i/o regoff iebus controller cassette deck unit tuner pack iebus driver/ receiver iebus cd unit cd changer, one cd, etc. dsp unit tv unit regc m pd784907, 784908 13 data sheet u11680ej2v0ds00 5. block diagram remark the internal rom and ram capacities differ depending on the product. nmi intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00 to p03 p04 to p07 pwm0 pwm1 intp5 reset test x1 x2 regc regoff ani0 to ani7 txd/so1 asck/sck1 rxd/si1 asck2/sck2 sck0 so0 si0 a8 to a15 p00 to p07 p20 to p27 p10 to p17 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 astb /clkout refrq/hldak wr wait/hldrq ad0 to ad7 rd a16 to a19 av dd v dd av ref1 av ss v ss uart/ioe2 baud-rate generator uart/ioe1 clocked serial interface clock output bus interface port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 programmable interrupt controller timer/counter 0 timer/counter 1 timer/counter 2 timer 3 real-time output port pwm a /d converter intp0 to intp5 (16 bits) (16 bits) (16 bits) (16 bits) rom 78k /iv cpu core watchdog timer baud-rate generator txd2/so2 rxd2/si2 tx rx iebus controller xt1 xt2 watch timer sck3 so3 si3 clocked serial interface 3 p90 to p97 p100 to p107 port 9 port 10 system control (regulator) ram m pd784907, 784908 14 data sheet u11680ej2v0ds00 port 3 (p3): ? 8-bit i/o port. ? input and output can be specified in 1-bit units. ? the use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. ? the use of the n-ch open drain can be specified for pins p32 and p33. 6. pin functions 6.1 port pins (1/2) pin name i/o alternate function function p00 to p07 i/o port 0 (p0): ? 8-bit i/o port. ? can be used as a real-time output port (4 bits 2). ? input and output can be specified by 1-bit units. ? the use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. ? can drive transistors. p10 i/o p11 p12 asck2/sck2 p13 rxd2/si2 p14 txd2/so2 p15 to p17 p20 input nmi p21 intp0 p22 intp1 p23 intp2/ci p24 intp3 p25 intp4/asck/sck1 p26 intp5 p27 si0 p30 i/o rxd/si1 p31 txd/so1 p32 sck0 p33 so0 p34 to p37 to0 to to3 p40 to p47 i/o ad0 to ad7 port 4 (p4): ? 8-bit i/o port. ? input and output can be specified in 1-bit units. ? the use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. ? can drive leds. p50 to p57 i/o a8 to a15 port 5 (p5): ? 8-bit i/o port. ? input and output can be specified in 1-bit units. ? the use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. ? can drive leds. port 2 (p2): ? 8-bit input port. ? p20 does not function as a general-purpose port (non-maskable interrupt). however, the input level can be checked by an interrupt service routine. ? the use of on-chip pull-up resistors can be specified by software for pins p22 to p27 (in 6-bit units). ? the p25/intp4/asck/sck1 pin functions as the sck1 output pin by a csim1 specification. port 1 (p1): ? 8-bit i/o port. ? input and output can be specified in 1-bit units. ? the use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. ? can drive leds. m pd784907, 784908 15 data sheet u11680ej2v0ds00 6.1 port pins (2/2) pin name i/o alternate function function p60 to p63 i/o a16 to a19 p64 rd p65 wr p66 wait/hldrq p67 refrq/hldak p70 to p77 i/o ani0 to ani7 port 7 (p7): ? 8-bit i/o port. ? input and output can be specified in 1-bit units. p90 to p97 i/o port 9 (p9): ? 8-bit i/o port. ? input and output can be specified in 1-bit units. ? the use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. p100 to i/o p104 p105 sck3 p106 si3 p107 so3 port 6 (p6): ? 8-bit i/o port. ? input and output can be specified in 1-bit units. ? the use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. port 10 (p10): ? 8-bit i/o port. ? input and output can be specified in 1-bit units. ? the use of on-chip pull-up resistors can be simultaneously specified by software for all pins in input mode. ? the use of the n-ch open drain can be specified for pins p105 and p107. m pd784907, 784908 16 data sheet u11680ej2v0ds00 6.2 non-port pins (1/2) pin name i/o alternate function function to0 to to3 output p34 to p37 timer output ci input p23/intp2 input of a count clock for timer/counter 2 rxd input p30/si1 serial data input (uart0) rxd2 p13/si2 serial data input (uart2) txd output p31/so1 serial data output (uart0) txd2 p14/so2 serial data output (uart2) asck input p25/intp4/sck1 baud rate clock input (uart0) asck2 p12/sck2 baud rate clock input (uart2) si0 input p27 serial data input (3-wire serial i/o 0) si1 p30/rxd serial data input (3-wire serial i/o 1) si2 p13/rxd2 serial data input (3-wire serial i/o 2) si3 p106 serial data input (3-wire serial i/o 3) so0 output p33 serial data output (3-wire serial i/o 0) so1 p31/txd serial data output (3-wire serial i/o 1) so2 p14/txd2 serial data output (3-wire serial i/o 2) so3 p107 serial data output (3-wire serial i/o 3) sck0 i/o p32 serial clock i/o (3-wire serial i/o 0) sck1 p25/intp4/asck serial clock i/o (3-wire serial i/o 1) sck2 p12/asck2 serial clock i/o (3-wire serial i/o 2) sck3 p105 serial clock i/o (3-wire serial i/o 3) nmi input p20 external interrupt intp0 p21 request ? input of a count clock for timer/counter 1 ? capture/trigger signal for cr11 or cr12 intp1 p22 ? input of a count clock for timer/counter 2 ? capture/trigger signal for cr22 intp2 p23/ci ? input of a count clock for timer/counter 2 ? capture/trigger signal for cr21 intp3 p24 ? input of a count clock for timer/counter 0 ? capture/trigger signal for cr02 intp4 p25/asck/sck1 intp5 p26 input of a conversion start trigger for a/d converter ad0 to ad7 i/o p40 to p47 time multiplexing address/data bus (for connecting external memory) a8 to a15 output p50 to p57 high-order address bus (for connecting external memory) a16 to a19 output p60 to p63 high-order address bus during address expansion (for connecting external memory) rd output p64 strobe signal output for reading the contents of external memory wr output p65 strobe signal output for writing on external memory wait input p66/hldrq wait insertion refrq output p67/hldak refresh pulse output to external pseudo static memory hldrq input p66/wait input of bus hold request hldak output p67/refrq output of bus hold response astb output clkout latch timing output of time multiplexing address (a0 to a7) (for connecting external memory) m pd784907, 784908 17 data sheet u11680ej2v0ds00 6.2 non-port pins (2/2) pin name i/o alternate function function clkout output astb clock output pwm0 output pwm output 0 pwm1 output pwm output 1 rx input data input (iebus) tx output data output (iebus) regc capacitance connection for stabilizing the regulator output/power supply when the regulator is stopped. connect to v ss via a capacitor of order of 1 m f. regoff signal for specifying regulator operation reset input chip reset x1 input crystal input for system clock oscillation (a clock pulse can also be input x2 to the x1 pin.) xt1 input watch clock connection xt2 ani0 to ani7 input p70 to p77 analog voltage input for a/d converter av ref1 to apply the reference voltage for a/d converter av dd positive power supply for a/d converter av ss gnd for a/d converter v dd positive power supply v ss gnd test input connect directly to v ss . (this pin is for ic test.) m pd784907, 784908 18 data sheet u11680ej2v0ds00 6.3 pin i/o circuits and recommended connections of unused pins the input/output circuit type of each pin and recommended connections of unused pins are shown in table 6-1. for each type of input/output circuit, refer to figure 6-1. table 6-1. types of pin i/o circuits and recommended connections of unused pins (1/2) pin name i/o circuit type i/o recommended connections of unused pins p00 to p07 5-a i/o input: connect to v dd p10, p11 output: leave open p12/asck2/sck2 8-a p13/rxd2/si2 5-a p14/txd2/so2 p15 to p17 p20/nmi 2 input connect to v dd or v ss p21/intp0 p22/intp1 2-a connect to v dd p23/intp2/ci p24/intp3 p25/intp4/asck/sck1 8-a i/o input: connect to v dd output: leave open p26/intp5 2-a input connect to v dd p27/si0 p30/rxd/si1 5-a i/o input: connect to v dd p31/txd/so1 output: leave open p32/sck0 10-a p33/so0 p34/to0 to p37/to3 5-a p40/ad0 to p47/ad7 p50/a8 to p57/a15 p60/a16 to p63/a19 p64/rd p65/wr p66/wait/hldrq p67/refrq/hldak p70/ani0 to p77/ani7 20 i/o input: connect to v dd or v ss p90 to p97 5-a output: leave open p100 to p104 p105/sck3 10-a p106/si3 8-a p107/so3 10-a astb/clkout 4 output leave open m pd784907, 784908 19 data sheet u11680ej2v0ds00 table 6-1. types of pin i/o circuits and recommended connections of unused pins (2/2) pin name i/o circuit type i/o recommended connections of unused pins reset 2 input test 1 connect directly to v ss xt2 leave open xt1 input connect to v ss pwm0, pwm1 3 output leave open rx 1 input connect to v dd or v ss tx 3 output leave open av ref1 connect to v ss av ss av dd connect to v dd caution connect an i/o pin, whose input/output mode is undefined, to v dd via a resistor of several 10 k w (especially if the voltage on the reset input pin rises higher than the low level input at power on or when the mode is being switched between input and output by software). remark since type numbers are commonly used in the 78k series, these numbers are not always serial in each product (some circuits are not included). m pd784907, 784908 20 data sheet u11680ej2v0ds00 type 1 type 4 type 5-a type 2 type 2-a type 8-a type 3 type 10-a in v dd p n data v dd p n out output disable push-pull output which can output high impedance (both the positive and negative channels are off.) in schmitt trigger input with hysteresis characteristics data v dd p n in/out output disable v dd p pull-up enable input enable schmitt trigger input with hysteresis characteristics in v dd p pull-up enable data v dd p n in/out output disable v dd p pull-up enable data out v dd p-ch n-ch data v dd p n in/out output disable v dd p pull-up enable open drain figure 6-1. i/o circuits for pins m pd784907, 784908 21 data sheet u11680ej2v0ds00 type 20 data comparator v dd v ref p (threshold voltage) p n n in/out output disable input enable + m pd784907, 784908 22 data sheet u11680ej2v0ds00 7. cpu architecture 7.1 memory space a memory space of 1 mbyte can be accessed. by using a location instruction, the mode for mapping internal data areas (special function registers and internal ram) can be selected. a location instruction must always be executed after a reset, and can be used only once. (1) when the location 0 instruction is executed ? internal memory the internal data area and internal rom area are mapped as follows: part number internal data area internal rom area m pd784907 0f100h to 0ffffh 00000h to 0f0ffh 10000h to 17fffh m pd784908 0ee00h to 0ffffh 00000h to 0fdffh 10000h to 1ffffh caution the following internal rom areas, existing at the same addresses as the internal data areas, cannot be used when the location 0 instruction is executed: part number unusable area m pd784907 0f100h to 0ffffh (3,840 bytes) m pd784908 0ee00h to 0ffffh (4,608 bytes) ? external memory the external memory is accessed in external memory expansion mode. (2) when the location 0fh instruction is executed ? internal memory the internal data area and internal rom area are mapped as follows: part number internal data area internal rom area m pd784907 ff100h to fffffh 00000h to 17fffh m pd784908 fee00h to fffffh 00000h to 1ffffh ? external memory the external memory is accessed in external memory expansion mode. m pd784907, 784908 23 data sheet u11680ej2v0ds00 figure 7-1. m pd784907 memory map notes 1. accessed in external memory expansion mode. 2. this 3,840-byte area can be used as an internal rom area only when the location 0fh instruction is executed. 3. when the location 0 instruction is executed: 94,464 bytes when the location 0fh instruction is executed: 98,304 bytes 4. base area and entry area based on a reset or interrupt. however, internal ram is not used as a reset entry area. fffffh 18000h 17fffh 0ffffh 0 ffdfh 0ffd0h 0ff00h 10000h 0feffh 0f100h 0f0ffh 00000h 0feffh 0fe80h 0fe7fh 0fe39h 0fe06h 0fd00h 0 fcffh 0f100h 17fffh 10000h 0f0ffh 01000h 00fffh 00800h 007ffh 00080h 0007fh 00040h 0003fh 00000h ffeffh ffe80h ffe7fh ffe39h ffe06h ffd00h ffcffh ff100h ff100h ff0ffh 18000h 17fffh 00000h ffeffh fffdfh fffd0h fff00h fffffh 17fffh when the location 0 instruction is executed external memory (928 kbytes) note 1 internal rom (32,768 bytes) special function registers (sfrs) note 1 (256 bytes) internal ram (3,584 bytes) internal rom (61,696 bytes) note 4 general-purpose registers (128 bytes) macro service control word area (42 bytes) data area (512 bytes) program/data area (3,072 bytes) program/data area note 3 note 2 callf entry area (2 kbytes) callt table area (64 bytes) vector table area (64 bytes) when the location 0fh instruction is executed internal ram (3,584 bytes) external memory (946,432 bytes) note 1 internal rom (96 kbytes) note 4 special function registers (sfrs) (256 bytes) note 1 m pd784907, 784908 24 data sheet u11680ej2v0ds00 figure 7-2. m pd784908 memory map notes 1. accessed in external memory expansion mode. 2. this 4,608-byte area can be used as an internal rom area only when the location 0fh instruction is executed. 3. when the location 0 instruction is executed: 126,464 bytes when the location 0fh instruction is executed: 131,072 bytes 4. base area and entry area based on a reset or interrupt. however, internal ram is not used as a reset entry area. fffffh 20000h 0ffffh 1ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 10000h 0ee0 0h 0edffh 00000h 0feffh 0fe80h 0fe7fh 0fe39h 0fe06h 0fd00h 0fcffh 0ee0 0h 1ffffh 10000h 0edffh 00800h 007ffh 01000h 00fffh 00080h 0007fh 00040h 0003fh 00000h ffeffh ffe8 0h ffe7fh ffe3 9h ffe0 6h ffd00h ffcffh fee0 0h fee0 0h fedffh ffeffh fff 0 0h fffd0h fffdfh fffffh 20000h 1ffffh 1ffffh 00000h when the location 0 instruction is executed external memory (896 kbytes) note 1 internal rom (65,536 bytes) special function registers (sfrs) note 1 (256 bytes) internal ram (4,352 bytes) note 4 internal rom (60,928 bytes) general-purpose registers (128 bytes) macro service control word area (42 bytes) data area (512 bytes) program/data area (3,840 bytes) note 2 program/data area note 3 callf entry area (2 kbytes) callt table area (64 bytes) vector table area (64 bytes) when the location 0fh instruction is executed special function registers (sfrs) note 4 internal rom (128 kbytes) external memory (912,896 bytes) note 1 internal ram (4,352 bytes) note 1 (256 bytes) m pd784907, 784908 25 data sheet u11680ej2v0ds00 a (r1) x (r0) b (r3) c (r2) r5 r4 r7 r6 r9 r8 r11 r10 d (r13) e (r12) h (r15) v u t w l (r14) ax (rp0) bc (rp1) rp2 rp3 vp (rp4) up (rp5) de (rp6) hl (rp7) vvp (rg4) uup (rg5) tde (rg6) whl (rg7) the character strings enclosed in parentheses represent absolute names. 8 banks 7.2 cpu registers 7.2.1 general-purpose registers a set of general-purpose registers consists of sixteen 8-bit general-purpose registers. two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers. eight banks of this register set are provided. the user can switch between banks by software or the context switching function. general-purpose registers other than the v, u, t, and w registers used for address extension are mapped onto internal ram. figure 7-3. general-purpose register format caution by setting the rss bit of psw to 1, r4, r5, r6, r7, rp2, and rp3 can be used as the x, a, c, b, ax, and bc registers, respectively. however, this function must be used only when using programs for the 78k/iii series. m pd784907, 784908 26 data sheet u11680ej2v0ds00 7.2.2 control registers (1) program counter (pc) this register is a 20-bit program counter. the program counter is automatically updated by program execution. figure 7-4. format of program counter (pc) 19 0 pc pswh pswl psw 15 14 13 12 uf rbs2 rbs1 rbs0 11 10 9 8 76543210 s z rss note ac ie p/v 0 cy 23 20 0 sp 0 0 0 0 (2) program status word (psw) this register holds the cpu state. the program status word is automatically updated by program execution. figure 7-5. format of program status word (psw) note this flag is used to maintain compatibility with the 78k/iii series. this flag must be set to 0 when programs for the 78k/iii series are not being used. (3) stack pointer (sp) this register is a 24-bit pointer for holding the start address of the stack. the higher 4 bits must be set to 0. figure 7-6. format of stack pointer (sp) m pd784907, 784908 27 data sheet u11680ej2v0ds00 7.2.3 special function registers (sfrs) the special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. the special function registers are mapped onto the 256-byte space between 0ff00h and 0ffffh note . note on execution of the location 0 instruction. fff00h to fffffh when the location 0fh instruction is executed. caution do not access an address in this area where no sfr is allocated, as the m pd784908 may be placed in the deadlock state. the deadlock state can be cleared only by a reset. table 7-1 lists the special function registers (sfrs). the symbols of the table columns are explained below. ? symbol .................................... symbol indicating an on-chip sfr. the symbols listed in the table are reserved words for the nec assembler (ra78k4). in the c compiler (cc78k4), the symbols can be used as sfr variables with the #pragma sfr command. ? r/w ......................................... indicates whether the sfr is read-only, write-only, or read/write. r/w: read/write r: read-only. w: write-only. ? bit units for manipulation ....... indicates the maximum number of bits that can be manipulated whenever an sfr is manipulated. an sfr that supports 16-bit manipulation can be described in the sfrp operand. for address specification, an even-numbered address must be specified. an sfr that can be manipulated in 1-bit units can be described as the operand of a bit manipulation instruction. ? after reset ............................... indicates the state of the register when the reset signal has been input. m pd784907, 784908 28 data sheet u11680ej2v0ds00 table 7-1. special function registers (sfrs) (1/5) address note special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w undefined 0ff01h port 1 p1 0ff02h port 2 p2 r 0ff03h port 3 p3 r/w 0ff04h port 4 p4 0ff05h port 5 p5 0ff06h port 6 p6 00h 0ff07h port 7 p7 undefined 0ff09h port 9 p9 0ff0ah port 10 p10 0ff0eh port 0 buffer register l p0l 0ff0fh port 0 buffer register h p0h 0ff10h compare register (timer/counter 0) cr00 0ff12h capture/compare register (timer/counter 0) cr01 0ff14h compare register l (timer/counter 1) cr10 cr10w 0ff15h compare register h (timer/counter 1) 0ff16h capture/compare register l (timer/counter 1) cr11 cr11w 0ff17h capture/compare register h (timer/counter 1) 0ff18h compare register l (timer/counter 2) cr20 cr20w 0ff19h compare register h (timer/counter 2) 0ff1ah capture/compare register l (timer/counter 2) cr21 cr21w 0ff1bh capture/compare register h (timer/counter 2) 0ff1ch compare register l (timer 3) cr30 cr30w 0ff1dh compare register h (timer 3) 0ff20h port 0 mode register pm0 ffh 0ff21h port 1 mode register pm1 0ff23h port 3 mode register pm3 0ff24h port 4 mode register pm4 0ff25h port 5 mode register pm5 0ff26h port 6 mode register pm6 0ff27h port 7 mode register pm7 0ff29h port 9 mode register pm9 0ff2ah port 10 mode register pm10 0ff2eh real-time output port control register rtpc 00h 0ff30h capture/compare control register 0 crc0 10h 0ff31h timer output control register toc 00h 0ff32h capture/compare control register 1 crc1 0ff33h capture/compare control register 2 crc2 10h note when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. m pd784907, 784908 29 data sheet u11680ej2v0ds00 address note special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ff36h capture register (timer/counter 0) cr02 r 0000h 0ff38h capture register l (timer/counter 1) cr12 cr12w 0ff39h capture register h (timer/counter 1) 0ff3ah capture register l (timer/counter 2) cr22 cr22w 0ff3bh capture register h (timer/counter 2) 0ff41h port 1 mode control register pmc1 r/w 00h 0ff43h port 3 mode control register pmc3 0ff4ah port 10 mode control register pmc10 0ff4eh register l for optional pull-up resistor puol 0ff4fh register h for optional pull-up resistor puoh 0ff50h timer register 0 tm0 r 0000h 0ff51h 0ff52h timer register 1 tm1 tm1w 0ff53h 0ff54h timer register 2 tm2 tm2w 0ff55h 0ff56h timer register 3 tm3 tm3w 0ff57h 0ff5ch prescaler mode register 0 prm0 r/w 11h 0ff5dh timer control register 0 tmc0 00h 0ff5eh prescaler mode register 1 prm1 11h 0ff5fh timer control register 1 tmc1 00h 0ff68h a/d converter mode register adm 00h 0ff6ah a/d conversion result register adcr r undefined 0ff6ch a/d current cut selection register iead r/w 00h 0ff6fh clock timer mode register wm 0ff70h pwm control register pwmc 05h 0ff71h pwm prescaler register pwpr 00h 0ff72h pwm modulo register 0 pwm0 undefined 0ff74h pwm modulo register 1 pwm1 0ff7dh one-shot pulse output control register ospc 00h 0ff80h clocked serial interface mode register 3 csim3 0ff82h clocked serial interface mode register csim table 7-1. special function registers (sfrs) (2/5) note when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. m pd784907, 784908 30 data sheet u11680ej2v0ds00 address note special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ff84h clocked serial interface mode register 1 csim1 r/w 00h 0ff85h clocked serial interface mode register 2 csim2 0ff86h serial shift register sio undefined 0ff88h asynchronous serial interface mode register asim 00h 0ff89h asynchronous serial interface mode register 2 asim2 0ff8ah asynchronous serial interface status register asis r 0ff8bh asynchronous serial interface status register 2 asis2 0ff8ch serial receive buffer: uart0 rxb undefined serial transmission shift register: uart0 txs w serial shift register: ioe1 sio1 r/w 0ff8dh serial receive buffer: uart2 rxb2 r serial transmission shift register: uart2 txs2 w serial shift register: ioe2 sio2 r/w 0ff8eh serial shift register 3: ioe3 sio3 0ff90h baud rate generator control register brgc 00h 0ff91h baud rate generator control register 2 brgc2 0ffa0h external interrupt mode register 0 intm0 0ffa1h external interrupt mode register 1 intm1 0ffa4h sampling clock selection register scs0 0ffa8h in-service priority register ispr r 0ffaah interrupt mode control register imc r/w 80h 0ffach interrupt mask register 0l mk0l mk0 ffffh 0ffadh interrupt mask register 0h mk0h 0ffaeh interrupt mask register 1l mk1l mk1 ffffh 0ffafh interrupt mask register 1h mk1h 0ffb0h bus control register bcr 00h 0ffb2h unit address register uar 0000h 0ffb4h slave address register sar 0ffb6h partner address register par r 0ffb8h control data register cdr r/w 01h 0ffb9h telegraph length register dlr table 7-1. special function registers (sfrs) (3/5) note applicable when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. m pd784907, 784908 31 data sheet u11680ej2v0ds00 address note special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ffbah data register dr r/w 00h 0ffbbh unit status register usr r 0ffbch interrupt status register isr r/w 0ffbdh slave status register ssr r 41h 0ffbeh success count register scr 01h 0ffbfh communication count register ccr 20h 0ffc0h standby control register stbc r/w note 2 30h 0ffc2h watchdog timer mode register wdm note 2 00h 0ffc4h memory expansion mode register mm 20h 0ffc5h hold mode register hldm 00h 0ffc6h clock output mode register clom 0ffc7h programmable wait control register 1 pwc1 aah 0ffc8h programmable wait control register 2 pwc2 aaaah 0ffcch refresh mode register rfm 00h 0ffcdh refresh area specification register rfa 0ffcfh oscillation stabilization time specification register osts 0ffd0h to external sfr area 0ffdfh 0ffe0h interrupt control register (intp0) pic0 43h 0ffe1h interrupt control register (intp1) pic1 0ffe2h interrupt control register (intp2) pic2 0ffe3h interrupt control register (intp3) pic3 0ffe4h interrupt control register (intc00) cic00 0ffe5h interrupt control register (intc01) cic01 0ffe6h interrupt control register (intc10) cic10 0ffe7h interrupt control register (intc11) cic11 0ffe8h interrupt control register (intc20) cic20 0ffe9h interrupt control register (intc21) cic21 0ffeah interrupt control register (intc30) cic30 0ffebh interrupt control register (intp4) pic4 0ffech interrupt control register (intp5) pic5 0ffedh interrupt control register (intad) adic 0ffeeh interrupt control register (intser) seric table 7-1. special function registers (sfrs) (4/5) notes 1. when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. 2. a write operation can be performed only with special instructions mov stbc,#byte and mov wdm,#byte. other instructions cannot perform a write operation. m pd784907, 784908 32 data sheet u11680ej2v0ds00 address note special function register (sfr) name symbol r/w bit units for manipulation after reset 1 bit 8 bits 16 bits 0ffefh interrupt control register (intsr) sric r/w 43h interrupt control register (intcsi1) csiic1 0fff0h interrupt control register (intst) stic 0fff1h interrupt control register (intcsi) csiic 0fff2h interrupt control register (intser2) seric2 0fff3h interrupt control register (intsr2) sric2 interrupt control register (intcsi2) csiic2 0fff4h interrupt control register (intst2) stic2 0fff6h interrupt control register (intie1) ieic1 0fff7h interrupt control register (intie2) ieic2 0fff8h interrupt control register (intw) wic 0fff9h interrupt control register (intcsi3) csiic3 0fffch internal memory size switching register note 2 ims ffh table 7-1. special function registers (sfrs) (5/5) notes 1. when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. 2. a write to this register is meaningful only for the m pd78p4908. m pd784907, 784908 33 data sheet u11680ej2v0ds00 8. peripheral hardware functions 8.1 ports the ports shown in figure 8-1 are provided to make various control operations possible. table 8-1 shows the functions of the ports. when inputting to port 0 to port 6, port 9, and port 10, an on-chip pull-up resistor can be specified by software. figure 8-1. port configuration port 0 p00 p07 8 port 4 p40 p47 port 1 p10 p17 port 2 p20 to p27 port 3 p30 p37 port 5 p50 p57 port 6 p60 p67 port 7 p70 p100 p77 port 9 p90 p97 port 10 p107 m pd784907, 784908 34 data sheet u11680ej2v0ds00 table 8-1. port functions port name pin name function specification of pull-up resistor connection by software port 0 p00 to p07 ? input or output mode can be specified all port pins in input mode in 1-bit units ? operable as 4-bit real-time outputs (p00 to p03, p04 to p07) ? can drive transistors port 1 p10 to p17 ? input or output mode can be specified all port pins in input mode in 1-bit units ? can drive leds port 2 p20 to p27 ? input port in 6-bit units (p22 through p27) port 3 p30 to p37 ? input or output mode can be specified all port pins in input mode in 1-bit units ? either pin p32/sck0 or p33/so0 can be set as the n-ch open drain. port 4 p40 to p47 ? input or output mode can be specified all port pins in input mode in 1-bit units ? can drive leds port 5 p50 to p57 ? input or output mode can be specified all port pins in input mode in 1-bit units ? can drive leds port 6 p60 to p67 ? input or output mode can be specified all port pins in input mode in 1-bit units port 7 p70 to p77 ? input or output mode can be specified in 1-bit units port 9 p90 to p97 ? input or output mode can be specified all port pins in input mode in 1-bit units port 10 p100 to p107 ? input or output mode can be specified all port pins in input mode in 1-bit units ? either pin p105/sck3 or p107/so3 can be set as the n-ch open drain. m pd784907, 784908 35 data sheet u11680ej2v0ds00 8.2 clock generator a circuit for generating the clock signal required for operation is provided. the clock generator has a frequency divider. if high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to reduce the current consumption. figure 8-2. block diagram of clock generator note set bit 7 of the standby control register (stbc) to 1. remark f xx : oscillator frequency or external clock input frequency f clk : internal operating frequency x1 x2 oscillator f xx f clk clock-synchronized 3-wire serial i/o (csi) asynchronous serial i/o (uart/ioe) intp0 noise eliminator oscillation settling timer timer/counter 1/2 1/2 1/2 f xx /8 f xx /4 f xx /2 selector selector stbc.4, 5 cpu peripheral circuits 1 0 stbc.7 operation clock of the iebus controller note watch clock main clock watch timer intw interrupt signal m pd784907, 784908 36 data sheet u11680ej2v0ds00 v ss x1 x2 pd784908 m pd784908 x1 x2 pd74hc04, etc. m m x1 x2 open pd784908 m figure 8-3. examples of using oscillator (1) crystal/ceramic oscillation (2) external clock ? when extc bit of osts = 1 ? when extc bit of osts = 0 caution when using the clock generator, wire in the area enclosed by the broken lines to avoid adverse influence from capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? make the ground point of the oscillator capacitor the same potential as v ss . do not ground the capacitor to a ground pattern in which a high current flows. ? do not fetch signals from the oscillator. m pd784907, 784908 37 data sheet u11680ej2v0ds00 x2 pd784908 m x1 v ss compared with the main system clock oscillator, the watch clock oscillator, which is a low-gain circuit designed to reduce current consumption, is more likely to cause noise-induced malfunctions. therefore, special care should be taken when using the watch clock oscillator. the microcontroller can operate normally only when the oscillation is normal and stable. if a high-precision oscillator frequency is required, consult with the oscillator manufacturer. figure 8-4. notes on connecting the oscillator cautions 1. place the oscillator as close as possible to pins x1 and x2 (xt1 and xt2). 2. do not let other signal lines cross that part of the circuit enclosed in broken lines. m pd784907, 784908 38 data sheet u11680ej2v0ds00 8.3 real-time output port the real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. thus, pulse output that is free of jitter can be obtained. therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors) where an arbitrary pattern is output at arbitrary intervals. as shown in figure 8-5, the real-time output port is built around port 0 and the port 0 buffer register (p0h, p0l). figure 8-5. block diagram of real-time output port 4 4 4 p0l p0h port 0 buffer register 8 4 8 p00 p07 output latch (p0) real-time output port control register (rtpc) output trigger control circuit intp0 (externally) intc10 (from timer/counter 1) intc11 (from timer/counter 1) internal bus m pd784907, 784908 39 data sheet u11680ej2v0ds00 8.4 timers/counters three timer/counter units and one timer unit are incorporated. moreover, because seven interrupt requests are supported, these timers/counters can be used as seven timer/ counter units. table 8-2. timers/counters operation name timer/counter 0 timer/counter 1 timer/counter 2 timer 3 item count width 8 bits 16 bits operating mode interval timer 2 ch 2 ch 2 ch 1 ch external event counter one-shot timer function timer output 2 ch 2 ch toggle output pwm/ppg output one-shot pulse output note real-time output pulse width measurement 1 input 1 input 2 inputs number of interrupt requests 2221 note the one-shot pulse output function makes the level of a pulse output active by software, and makes the level of a pulse output inactive by hardware (interrupt request signal). note that this function differs from the one-shot timer function of timer/counter 2. m pd784907, 784908 40 data sheet u11680ej2v0ds00 f xx /4 timer register 3 (tm3/tm3w) compare register (cr30/cr30w) prescaler uart, csi clear match intc30 figure 8-6. timer/counter block diagram timer/counter 0 timer/counter 1 timer/counter 2 timer 3 remark ovf: overflow flag to1 f xx /4 ovf to0 intp3 intp3 intc00 intc01 clear control prescaler selector timer register 0 (tm0) software trigger compare register (cr00) match match pulse output control compare register (cr01) edge detection capture register (cr02) f xx /4 ovf intp0 intp0 intc10 intc11 clear control prescaler selector timer register 1 (tm1/tm1w) event input compare register (cr10/cr10w) match match edge detection capture/compare register (cr11/cr11w) to real-time output port capture register (cr12/cr12w) to3 f xx /4 ovf to2 intp1 intp1 intc20 intc21 intp2/ci intp2 clear control prescaler selector timer register 2 (tm2/tm2w) edge detection edge detection compare register (cr20/cr20w) match match capture/compare register (cr21/cr21w) pulse output control capture register (cr22/cr22w) m pd784907, 784908 41 data sheet u11680ej2v0ds00 8.5 watch timer as the count clock, either of two types of clock can be input to the watch timer: the main clock (6.29 mhz/12.58 mhz) or the watch clock (32.768 khz). they can be selected using the control register. the watch clock is input to the watch timer only. it is not input to the cpu or other peripheral circuits. therefore, the speed of cpu operation cannot be slowed by the watch clock. the watch timer generates interrupt signals (intw), at 0.5-second intervals note , by dividing the count clock. at the same time, the watch timer sets the interrupt request flag (wif) (where wif refers to bit 7 of the interrupt control register (wic)). by switching modes, the intw generation interval can be changed to about 1 ms (fast-forward mode: normal operation speed 512). when the main clock is selected as the count clock, the watch timer stops if in stop or idle standby mode, but continues operating if in halt standby mode. when the watch clock is selected as the count clock, the watch timer continues operating regardless of the standby mode. the operation of the watch clock oscillator is controlled by means of the watch timer mode register (wm). the watch timer of the m pd784908 does not have a buzzer output function. note after the operation is enabled, the time until first intw generation is not 0.5 s. table 8-3. relationship between count clock and watch timer operation count clock selection normal operation mode standby modes halt mode stop mode idle mode main clock operable operable stopped stopped watch clock operable operable operable operable the watch timer consists of a frequency divider which divides the count clock by 3 and a counter which divides the frequency output from the frequency divider by 2 14 . as the count clock, select the signal obtained by dividing the internal system clock by 128 or that output by the watch clock oscillator. figure 8-7. watch timer block diagram on/off wm.7 wm.6 0 1 0 1 0 1 sel sel sel 12 34 5 6 789 10111213 14 wm.2 intw stbc.7 wm.3 reset main clock f xx /128 division by 3 counter counter watch clock oscillator main clock selection: 6.29 mhz 12.58 mhz m pd784907, 784908 42 data sheet u11680ej2v0ds00 8.6 pwm output (pwm0, pwm1) two channels of pwm (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 24.57 khz (fclk = 6.29 mhz) are incorporated. low or high active level can be selected for the pwm output channels, independently of each other. this output is best suited to dc motor speed control. figure 8-8. block diagram of pwm output unit (modulo register) pwm control register (pwmc) reload control prescaler 8-bit down-counter pulse control circuit 4-bit counter output control pwmn (output pin) 1/256 f clk 84 16 8 pwmn 15 0 8 7 4 3 internal bus remark n = 0, 1 m pd784907, 784908 43 data sheet u11680ej2v0ds00 8.7 a/d converter an analog/digital (a/d) converter having 8 multiplexed analog inputs (ani0 through ani7) is incorporated. the successive approximation system is used for conversion. the result of conversion is held in the 8-bit a/d conversion result register (adcr). thus, speedy high-precision conversion can be achieved. a/d conversion can be started in the following two ways: ? hardware start: conversion is started by trigger input (intp5). ? software start: conversion is started by setting the bit of the a/d converter mode register (adm). after conversion has started, one of the following modes can be selected: ? scan mode: multiple analog inputs are selected sequentially to convert multiple pins. ? select mode: a single analog input is selected at all times to enable conversion data to be obtained continuously. adm is used to specify the above modes, as well as the termination of conversion. when the result of conversion is transferred to adcr, an interrupt request (intad) is generated. using this feature, the results of conversion can be continuously transferred to memory by the macro service. cautions 1. for this product, apply the same voltage as the power supply voltage (av dd ) to the reference voltage input pin (av ref1 ). 2. when port 7 is used as both an output port and a/d input line, do not manipulate the output port while a/d conversion is in progress. figure 8-9. block diagram of a/d converter ani0 ani7 intp5 av ref1 av ss r/2 r r/2 8 8 8 input selector tap selector sample and hold circuit voltage comparator successive approximation register (sar) connection control a/d current cut selection register (iead) series resistor string control circuit a/ d converter mode register (adm) a/ d conversion result register (adcr) internal bus edge detection circuit conversion trigger trigger enable intad ani1 ani2 ani3 ani4 ani5 ani6 av dd m pd784907, 784908 44 data sheet u11680ej2v0ds00 8.8 serial interface four independent serial interface channels are incorporated. ? asynchronous serial interface (uart)/3-wire serial i/o (ioe) 2 ? synchronous serial interface (csi) 2 ? 3-wire serial i/o (ioe) this makes it possible for communication with an external system and local communication within the system to be simultaneously executed (see figure 8-10 ). figure 8-10. example of serial interface si so sck port int v dd uart + 3-wire serial i/o + 2-wire serial i/o [3-wire serial i/o] [2-wire serial i/o] rs-232-c driver/receiver port rxd txd so1 si1 sck1 intpm port si0 so0 sck0 intpn port note slave slave pd784908 (master) m sb0 sck0 port int note pd4711a m [uart] v dd note handshake line m pd784907, 784908 45 data sheet u11680ej2v0ds00 rxb, rxb2 txs, txs2 intst, intst2 intsr, intsr2 intser, intser2 1/2m f xx asck, asck2 txd, txd2 rxd, rxd2 1/2 n+1 1/2m baud rate generator receive shift register receive buffer selector transmission control parity bit addition transmission shift register internal bus reception control parity check 8.8.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) two serial interface channels, from which asynchronous serial interface mode and 3-wire serial i/o mode can be selected, are provided. (1) asynchronous serial interface mode in this mode, 1-byte data is transferred or received after a start bit. a baud rate generator is incorporated to enable communication at a wide range of baud rates. a baud rate can be defined by dividing the frequency of a clock signal input to the asck pin. by using the baud rate generator, a baud rate conforming to the midi standard (31.25 kbps) can be obtained. figure 8-11. block diagram of asynchronous serial interface mode remark f xx : oscillating frequency or external clock input frequency n = 0 to 11 m = 16 to 30 m pd784907, 784908 46 data sheet u11680ej2v0ds00 serial clock counter sio1, sio2 si1, si2 so1, so2 sck1, sck2 f xx intcsi1, intcsi2 shift register output latch direction control circuit internal bus serial clock control circuit selector 1/m 1/2 n+1 interrupt generator (2) 3-wire serial i/o mode in this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in synchronization with this clock. this mode is designed for communication with a device incorporating a conventional synchronous serial interface. basically, three lines are used for communication: the serial clock line (sck) and the two serial data lines (si and so). in general, a handshake line is required to check the state of communication. figure 8-12. block diagram of 3-wire serial i/o mode remark f xx : oscillating frequency or external clock input frequency n = 0 to 11 m = 1, 16 to 30 m pd784907, 784908 47 data sheet u11680ej2v0ds00 sin son sckn intcsin f xx /8 f xx /16 f xx /32 f xx /64 f xx /128 internal bus selector selector sion register csimn register serial clock counter 8.8.2 clocked serial interface (csi) with this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in synchronization with this clock. figure 8-13. block diagram of clocked serial interface remark f xx : oscillating frequency or external clock input frequency n = 0, 3 m pd784907, 784908 48 data sheet u11680ej2v0ds00 clkout f clk f clk /2 f clk /4 f clk /8 f clk /16 selector output control enable output output level ? 3-wire serial i/o mode this mode is designed for communication with a device incorporating a conventional clocked serial interface. basically, three lines are used for communication: the serial clock line (sckn) and serial data lines (sin and son) (n = 0, 3). in general, a handshake line is required to check the state of communication. 8.9 clock output function the frequency of the cpu clock signal can be divided and output from the system. moreover, the port can be used as a 1-bit port. the astb pin is also used as the clkout pin, so that when this function is used, the local bus interface cannot be used. figure 8-14. block diagram of clock output function m pd784907, 784908 49 data sheet u11680ej2v0ds00 8.10 edge detection function the interrupt input pins (nmi, intp0 through intp5) are used not only to input interrupt requests but also to input trigger signals to the internal hardware units. because these pins operate at the edge of the input signal, they have an edge-detection function incorporated. moreover, a noise elimination function is also provided to prevent erroneous edge detection caused by noise. table 8-4. noise elimination method of interrupt input pins pin name detectable edge noise elimination method nmi rising edge or falling edge analog delay intp0 to intp3 rising edge or falling edge, or both edges clock sampling note intp4, intp5 analog delay note intp0 is used for sampling clock selection. 8.11 watchdog timer a watchdog timer is incorporated to detect a cpu runaway. the watchdog timer, if not cleared by software within a specified interval, generates a non-maskable interrupt request. furthermore, once watchdog timer operation is enabled, it cannot be disabled by software. the user can specify whether priority is placed on an interrupt request based on the watchdog timer or on an interrupt request based on the nmi pin. figure 8-15. block diagram of watchdog timer f clk /2 21 f clk intwdt f clk /2 20 f clk /2 19 f clk /2 17 timer clear signal selector m pd784907, 784908 50 data sheet u11680ej2v0ds00 8.12 simplified iebus controller a newly developed iebus controller is incorporated into the m pd784908. this iebus controller has fewer functions than the iebus interface function of previous product (incorporated into the 78k/0). table 8-5 compares the previous product and the new, simplified iebus interface. table 8-5. comparisons between previous product and simplified iebus interface item previous product (iebus incorporated into 78k/0) simplified iebus communication mode modes 0 to 2 fixed to mode 1 internal system clock 6.0 (6.29) mhz internal buffer size transmission buffer 33 bytes (fifo) transmission/reception data register 1 byte reception buffer 40 bytes (fifo) up to four frames can be received cpu processing processing before transmission start (data setting) processing before transmission start (data setting) setting and control of each communication status setting and control of each communication status data write to the transmission buffer data write processing for every byte data read from the reception buffer data read processing for every byte transmission control such as slave status control of multiple frames, remastering request hardware processing bit processing bit processing (modulation/demodulation, error detection) (modulation/demodulation, error detection) field processing (generation, control) field processing (generation, control) detection of arbitration results detection of arbitration results parity processing (generation, error detection) parity processing (generation, error detection) ack/nack automatic response ack/nack automatic response automatic data retransmitting automatic data retransmitting automatic remastering transmission such as automatic slave status reception of multiple frames m pd784907, 784908 51 data sheet u11680ej2v0ds00 figure 8-16. iebus controller cpu interface section 88 8 8 8888 888 5 8 88 8 8 8 12 12 12 888 12 12 12 12 bcr(8) dlr(8) usr(8) isr(8) ssr(8) scr(8) ccr(8) dr(8) uar(12) sar(12) par(12) cdr(8) internal register section internal bus rx tx clk nf mpx mpx tx/rx psr (8 bits) 12-bit latch comparator interrupt control circuit int request (vector, macro service) interrupt control section parity error detector conflict detector ack generator iebus interface section bit processing section field processing section internal bus r/w m pd784907, 784908 52 data sheet u11680ej2v0ds00 ? hardware configuration and functions the internal configuration of the iebus consists mainly of the following six sections: ? cpu interface section ? interrupt control section ? internal register section ? bit processing section ? field processing section ? iebus interface section m pd784907, 784908 53 data sheet u11680ej2v0ds00 9. interrupt function the three types of interrupt request-response servicing, as shown in table 9-1 below, can be selected by program. table 9-1. servicing of interrupt request servicing mode servicing agent servicing pc and psw contents vectored interrupt software branches and executes a servicing routine saves to and restores from the stack. (servicing is arbitrary). context switching automatically switches register banks, and saves to or restores from fixed area in branches and executes a servicing routine the register bank. (servicing is arbitrary). macro service firmware executes data transfer between memory and maintained i/o (servicing is fixed). 9.1 interrupt source table 9-2 shows the interrupt sources available. as shown, interrupts are generated by 27 types of sources, execution of the brk and brkcs instructions, or an operand error. four levels of interrupt servicing priority can be set. priority levels can be set to nest control during interrupt servicing or to simultaneously generate interrupt requests. however, nested macro services are performed without suspension. when interrupt requests having the same priority level are generated, they are serviced according to the default priority (fixed) (see table 9-2 ). m pd784907, 784908 54 data sheet u11680ej2v0ds00 table 9-2. interrupt source type default source internal/ macro priority name trigger external service software brk instruction instruction execution brkcs instruction instruction execution operand error when the mov stbc,#byte, mov wdm,#byte, or location instruction is executed, exclusive or of the byte operand and byte does not produce ffh. non-maskable nmi detection of edge input on the pin external wdt watchdog timer overflow internal maskable 0 (highest) intp0 detection of edge input on the pin (tm1/tm1w capture trigger) external ? 1 intp1 detection of edge input on the pin (tm2/tm2w capture trigger) 2 intp2 detection of edge input on the pin (tm2/tm2w event counter input) 3 intp3 detection of edge input on the pin (tm0 capture trigger) 4 intc00 tm0-cr00 match signal issued internal ? 5 intc01 tm0-cr01 match signal issued 6 intc10 tm1-cr10 match signal issued (in 8-bit operation mode) tm1w-cr10w match signal issued (in 16-bit operation mode) 7 intc11 tm1-cr11 match signal issued (in 8-bit operation mode) tm1w-cr11w match signal issued (in 16-bit operation mode) 8 intc20 tm2-cr20 match signal issued (in 8-bit operation mode) tm2w-cr20w match signal issued (in 16-bit operation mode) 9 intc21 tm2-cr21 match signal issued (in 8-bit operation mode) tm2w-cr21w match signal issued (in 16-bit operation mode) 10 intc30 tm3-cr30 match signal issued (in 8-bit operation mode) tm3w-cr30w match signal issued (in 16-bit operation mode) 11 intp4 detection of edge input on the pin external ? 12 intp5 detection of edge input on the pin (a/d converter start conversion trigger) 13 intad a/d converter processing completed (adcr transfer) internal ? 14 intser asi0 reception error 15 intsr asi0 reception completed or csi1 transfer completed ? intcsi1 16 intst asi0 transmission completed 17 intcsi csi0 transfer completed 18 intser2 asi2 reception error 19 intsr2 asi2 reception completed or csi2 transfer completed ? intcsi2 20 intst2 asi2 transmission completed 21 intie1 iebus data access request 22 intie2 iebus communication error and communication start/end 23 intw clock timer output 24 (lowest) intcsi3 csi3 transfer completed remark asi: asynchronous serial interface csi: clocked serial interface m pd784907, 784908 55 data sheet u11680ej2v0ds00 interrupt source vector table address brk instruction 003eh operand error 003ch nmi 0002h wdt 0004h intp0 0006h intp1 0008h intp2 000ah intp3 000ch intc00 000eh intc01 0010h intc10 0012h intc11 0014h intc20 0016h intc21 0018h intc30 001ah intp4 001ch intp5 001eh intad 0020h intser 0022h intsr 0024h intcsi1 intst 0026h intcsi 0028h intser2 002ah intsr2 002ch intcsi2 intst2 002eh 9.2 vectored interrupt when a branch to an interrupt servicing routine occurs, the vector table address corresponding to the interrupt source is used as the branch address. interrupt servicing by the cpu consists of the following operations : ? when branching: saves the cpu status (pc and psw contents) to the stack. ? when returning: restores the cpu status (pc and psw contents) from the stack. to return control from the servicing routine to the main routine, the reti instruction is used. the branch destination addresses must be within the range of 0 to ffffh. table 9-3. vector table address interrupt source vector table address ntie1 0032h intie2 0034h intw 0036h intcsi3 0038h m pd784907, 784908 56 data sheet u11680ej2v0ds00 cpu sfr memory read write read write macro service controller internal bus 9.3 context switching when an interrupt request is generated, or when the brkcs instruction is executed, a predetermined register bank is selected by the hardware. then, a branch to a vector address stored in that register bank occurs. at the same time, the contents of the current program counter (pc) and program status word (psw) are stacked in the register bank. the branch address must be within the range of 0 to ffffh. figure 9-1. context switching operation when interrupt request is generated 9.4 macro service the macro service function enables data transfer between memory and special function registers (sfrs) without requiring the intervention of the cpu. the macro service controller accesses both memory and sfrs within the same transfer cycle to directly transfer data without having to perform data fetch. since the cpu status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible. figure 9-2. macro service psw pc19-16 0000b pc15-0 exchange save save <2> <3> <4> <5> save <1> <6> <7> transfer (bits 8 to 11 of temporary register) register bank n (n = 0-7) temporary register ax bc r5 r4 r7 vp up r6 de h t u v wl switching between register banks (rbs0-rbs2 ? n) rss ? 0 ie ? 0 register bank (0 to 7) m pd784907, 784908 57 data sheet u11680ej2v0ds00 9.5 examples of macro service applications (1) serial interface transmission each time macro service request (intst) is generated, the next transmit data is transferred from memory to txs. when data n (last byte) has been transferred to txs (that is, once the transmit data storage buffer becomes empty), vectored interrupt request (intst) is generated. (2) serial interface reception each time macro service request (intsr) is generated, receive data is transferred from rxb to memory. when data n (last byte) has been transferred to memory (that is, once the receive data storage buffer becomes full), vectored interrupt request (intsr) is generated. transmit data storage buffer (memory) intst txs (sfr) txd data n data n - 1 data 2 data 1 internal bus transmit shift register transmit control receive data storage buffer (memory) intsr rxb (sfr) rxd data n data n - 1 data 2 data 1 internal bus receive buffer receive shift register receive control m pd784907, 784908 58 data sheet u11680ej2v0ds00 (3) real-time output port intc10 and intc11 function as the output triggers for the real-time output ports. for these triggers, the macro service can simultaneously set the next output pattern and interval. therefore, intc10 and intc11 can be used to independently control two stepping motors. they can also be applied to pwm and dc motor control. each time macro service request (intc10) is generated, a pattern and timing data are transferred to the buffer register (p0l) and compare register (cr10), respectively. when the contents of timer register 1 (tm1) and cr10 match, another intc10 is generated, and the p0l contents are transferred to the output latch. when tn (last byte) is transferred to cr10, vectored interrupt request (intc10) is generated. for intc11, the same operation as that performed for intc10 is performed. match (sfr) intc10 p00 to p03 (sfr) output pattern profile (memory) output timing profile (memory) p n p n? p 2 p 1 internal bus p0l output latch cr10 tm1 internal bus t n t n? t 2 t 1 m pd784907, 784908 59 data sheet u11680ej2v0ds00 10. local bus interface the local bus interface enables the connection of external memory and i/o devices (memory mapped i/o) and supports a 1-mbyte memory space (see figure 10-1 ). figure 10-1. example of local bus interface 10.1 memory expansion by adding external memory, program memory or data memory can be expanded, 256 bytes at a time, to approximately 1 mbyte (seven steps). data bus latch gate array for i/o expansion including centronics interface circuit, etc. rd wr refrq ad0 to ad7 astb pseudo sram prom pd27c1001a pd784908 a16 to a19 m m address bus a8 to a15 decoder kanji character generator pd24c1000 m m pd784907, 784908 60 data sheet u11680ej2v0ds00 fffffh 80000h 7ffffh 40000h 3ffffh 20000h 1ffffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 04000h 03fffh 00000h 512 kbytes 256 kbytes 128 kbytes 64 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes 10.2 memory space the 1-mbyte memory space is divided into eight spaces, each having a logical address. each of these spaces can be controlled using the programmable wait and pseudo-static ram refresh functions. figure 10-2. memory space m pd784907, 784908 61 data sheet u11680ej2v0ds00 10.3 programmable wait when the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the rd or wr signal is active. this prevents the overall system efficiency from being degraded even when memory devices having different access times are connected. in addition, an address wait function that extends the astb signal active period is provided to ensure the lapse of the address decode time. (this function is set for the entire space.) 10.4 pseudo-static ram refresh function refresh is performed as follows: ? pulse refresh a bus cycle is inserted where a refresh pulse is output on the refrq pin at regular intervals. when the memory space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the refrq pin as the memory is being accessed. this can prevent the refresh cycle from suspending normal memory access. ? power-down self-refresh in standby mode, a low-level signal is output on the refrq pin to maintain the contents of pseudo-static ram. 10.5 bus hold function a bus hold function is provided to facilitate connection to devices such as a dma controller. when a bus hold request signal (hldrq) is received from an external bus master, the address bus, address/data bus, and astb, rd, and wr pins enter the high-impedance state, the bus hold acknowledge signal (hldak) is made active, and the bus is released to the external bus master as soon as the current bus cycle is completed. while the bus hold function is being used, the external wait and pseudo-static ram refresh functions are disabled. m pd784907, 784908 62 data sheet u11680ej2v0ds00 11. standby function this function is to reduce the power consumption of the chip, and can be used in the following modes: ? halt mode: stops the operating clock of the cpu. this mode is used in combination with the normal operation mode for intermittent operation to reduce the average power consumption. ? idle mode: stops the entire system with the oscillator continuing operation. the power consumption in this mode is close to that in the stop mode. however, the time required to restore the normal program operation from this mode is almost the same as that from the halt mode. ? stop mode: stops the oscillator and thereby stops all the internal operations of the chip. consequently, the power consumption is minimized with only leakage current flowing. these modes are programmable. the macro service can be started from the halt mode. figure 11-1. standby mode status transition notes 1. intw, intp4, and intp5 are applied when not masked. 2. only unmasked interrupt request 3. when the watch clock is operating remark nmi is valid only for an external input. the watchdog timer cannot be used for the release of standby (stop, halt, or idle mode). stop (standby) idle (standby) request for masked interrupt halt (standby) intw notes 1, 3 nmi, intp4, intp5 input note 1 set stop reset input set idle reset input intw notes 1, 3 nmi, intp4, intp5 input note 1 oscillation settling time elapses wait for oscillation settling program operation macro service request end of one operation end of macro service macro service set halt reset input interrupt request note 2 macro service request end of one operation m pd784907, 784908 63 data sheet u11680ej2v0ds00 12. reset function when a low-level signal is input to the reset pin, the internal hardware becomes initialize status (reset status). when the reset input makes a low-to-high transition, the following data is loaded into the program counter (pc): ? low-order 8 bits of the pc: contents of address 0000h ? intermediate 8 bits of the pc: contents of address 0001h ? high-order 4 bits of the pc: 0 the pc contents are used as a branch destination address, and program execution starts from that address. therefore, a reset start can be performed from an arbitrary address. the contents of each register can be set by software, as necessary. the reset input circuit incorporates a noise eliminator to prevent malfunctions caused by noise. this noise eliminator is an analog delay sampling circuit. figure 12-1. accepting reset for power-on reset, the reset signal must be held active until the oscillation stabilization time (approximately 40 ms) has elapsed. figure 12-2. power-on reset reset (input) delay delay delay initialize pc execute instruction of reset start address internal reset signal start reset end reset oscillation stabilization time delay initialize pc execute instruction of reset start address reset (input) internal reset signal end reset v dd m pd784907, 784908 64 data sheet u11680ej2v0ds00 13. regulator the m pd784908 incorporates a regulator (a circuit which enables low-voltage operation) to reduce the current consumption of the device. to enable or disable the operation of this regulator, specify the input level of the regoff pin. to disable the operation of the regulator, input a high level signal to the regoff pin. to enable operation, input a low level signal to the regoff pin. when the regulator is turned on, the cpu enters low-power mode. it is recommended to operate this product using this regulator. to stabilize the regulator output voltage, connect a capacitor (of about 1 m f) to the regc pin (stabilizing capacitor connection pin). when the regulator is stopped, apply the same level as v dd to the regc pin. figure 13-1 is a block diagram of the regulator's peripheral circuits. figure 13-1. regulator peripheral circuits ? processing for the regc pin when the regulator is operating connect a capacitor to stabilize the regulator. when the regulator is stopped supply the power supply voltage. regoff v dd stbc.7 regc 1 f low level: regulator is turned on. high level: regulator is turned off. regulator internal power supply voltage (supplies to the cpu and peripheral circuits.) stops oscillation. m m pd784907, 784908 65 data sheet u11680ej2v0ds00 14. instruction set (1) 8-bit instructions (the instructions in parentheses are combinations realized by describing a as r) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chkl, chkla table 14-1. instruction list by 8-bit addressing 2nd operand #byte a r saddr sfr !addr16 mem r3 [whl+] n none note 2 r' saddr' !!addr24 [saddrp] pswl [whlC] 1st operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) notes 1, 6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop chkl chkla !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 [tdeC] (add) note 1 movm note 4 notes 1. addc, sub, subc, and, or, xor, and cmp are the same as add. 2. there is no second operand, or the second operand is not an operand address. 3. rol, rorc, rolc, shr, and shl are the same as ror. 4. xchm, cmpme, cmpmne, cmpmnc, and cmpmc are the same as movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are the same as movbk. 6. when saddr is saddr2 with this combination, an instruction with a short code exists. m pd784907, 784908 66 data sheet u11680ej2v0ds00 (2) 16-bit instructions (the instructions in parentheses are combinations realized by describing ax as rp) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 14-2. instruction list by 16-bit addressing 2nd operand #word ax rp saddrp sfrp !addr16 mem [whl+] byte n none note 2 rp' saddrp' !!addr24 [saddrp] 1st operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (add) note 1 (addw) note 1 (addw) notes 1,3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw notes 1. subw and cmpw are the same as addw. 2. there is no second operand, or the second operand is not an operand address. 3. when saddrp is saddrp2 with this combination, an instruction with a short code exists. 4. muluw and divux are the same as mulw. m pd784907, 784908 67 data sheet u11680ej2v0ds00 (3) 24-bit instructions (the instructions in parentheses are combinations realized by describing whl as rg) movg, addg, subg, incg, decg, push, pop table 14-3. instruction list by 24-bit addressing 2nd operand #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note 1st operand rg' whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note there is no second operand, or the second operand is not an operand address. m pd784907, 784908 68 data sheet u11680ej2v0ds00 (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 14-4. bit manipulation instruction list by addressing 2nd operand cy saddr.bit sfr.bit /saddr.bit /sfr.bit none note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit 1st operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note there is no second operand, or the second operand is not an operand address. m pd784907, 784908 69 data sheet u11680ej2v0ds00 (5) call/return instructions and branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 14-5. instruction list by call/return and branch instruction addressing instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none address operand basic bc note call call call call call call call callf callf brkcs brk instruction br br br br br br br br ret retcs reti retcsb retb compound bf instruction bt btclr bfset dbnz note bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not ei, di, swrs m pd784907, 784908 70 data sheet u11680ej2v0ds00 15. electrical specifications absolute maximum ratings (t a = 25 c) parameter symbol conditions ratings unit supply voltage v dd C0.3 to +6.5 v av dd C0.3 to v dd + 0.3 v av ss C0.3 to +0.3 v input voltage v i1 C0.3 to v dd + 0.3 v analog input voltage v an av ss C 0.3 to av ref1 + 0.3 v output voltage v o C0.3 to v dd + 0.3 v output current, low i ol per pin 10 ma total of p00 to p07, p30 to 50 ma p37, p54 to p57, p60 to p67, and p100 to p107 pins total of p10 to p17, p40 to 50 ma p47, p50 to p53, p70 to p77, p90 to p97, pwm0, pwm1, and tx pins output current, high i oh per pin C6 ma total of p00 to p07, p30 to C30 ma p37, p54 to p57, p60 to p67, and p100 to p107 pins total of p10 to p17, p40 to C30 ma p47, p50 to p53, p70 to p77, p90 to p97, pwm0, pwm1, and tx pins a/d converter reference input av ref1 C0.3 to v dd + 0.3 v voltage operating ambient temperature t a C40 to +85 c storage temperature t stg C65 to +150 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. remark unless otherwise specified, the characteristics of a alternate-function pin are the same as those of a port pin. m pd784907, 784908 71 data sheet u11680ej2v0ds00 capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 15 pf output capacitance c o unmeasured pins returned to 0 v. 15 pf i/o capacitance c io 15 pf 10,000 4,000 1,000 159 100 79 10 01234567 guaranteed operating range power supply voltage [v] clock cycle time t cyk [ns] operating conditions ? operating ambient temperature (t a ): C40 c to +85 c ? power supply voltage and clock cycle time: see figure 15-1 . ? selection of internal regulator (regoff pin: low-level input) figure 15-1. power supply voltage and clock cycle time m pd784907, 784908 72 data sheet u11680ej2v0ds00 main oscillator characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit oscillator frequency f xx ceramic resonator or crystal resonator 2 12.58 mhz caution when using the clock generator, wire to avoid adverse influence from wiring capacitance. ? keep the wiring length as short as possible. ? do not cross the wiring with other signal lines. ? do not route the wiring near a signal line through which a high fluctuating current flows. ? make the ground point of the oscillator capacitor the same potential as v ss1 . do not ground the capacitor to a ground pattern in which a high current flows. ? do not fetch signals from the oscillator. remark connect a 12.582912 mhz or 6.291456 mhz oscillator to operate the internal clock timer with the main clock. clock oscillator characteristics (t a = C40 to +85 c, v dd = 3.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit oscillator frequency f xt ceramic resonator or crystal resonator 32 32.768 35 khz oscillation stabilization t sxt v dd = 4.5 to 5.5 v 1.2 2 s time 10 s oscillation hold voltage v ddxt 3.5 5.5 v watch timer operating v ddw 3.5 5.5 v voltage m pd784907, 784908 73 data sheet u11680ej2v0ds00 dc characteristics (t a = C40 to +85 c, v dd = av dd = 3.5 to 5.5 v, v ss = av ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit input voltage, low note 5 v il1 for pins other than notes 1 and 2 C0.3 0.3v dd v v il2 for pins described in note 1 C0.3 0.2v dd v v il3 v dd = 4.5 to 5.5 v C0.3 +0.8 v for pins described in note 2 input voltage, high v ih1 for pins other than notes 1 and 2 0.7v dd v dd + 0.3 v v ih2 for pins described in note 1 0.8v dd v dd + 0.3 v v ih3 v dd = 4.5 to 5.5 v 2.2 v dd + 0.3 v for pins described in note 2 output voltage, low v ol1 i ol = 20 m a 0.1 v i ol = 100 m a 0.2 v i ol = 2 ma 0.4 v v ol2 i ol = 8 ma 1.0 v for pins described in note 4 v dd = 4.5 to 5.5 v output voltage, high v oh1 i oh = C20 m av dd C 0.1 v i oh = C100 m av dd C 0.2 v i oh = C2 ma v dd C 0.4 v v oh2 v dd = 4.5 to 5.5 v v dd C 1.0 v i oh = C5 ma for pins described in note 3 notes 1. x1, x2, reset, p12/asck2/sck2, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p32/sck0, p33/so0, p105/sck3, p106/si3, p107/so3, xt1, xt2 2. p40/ad0 to p47/ad7, p50/a8 to p57/a15, p60/a16 to p67/refrq/hldak, p00 to p07 3. p00 to p07 4. p10 to p17, p40/ad0 to p47/ad7, p50/a8 to p57/a15 5. other than pull-up resistors m pd784907, 784908 74 data sheet u11680ej2v0ds00 dc characteristics (t a = C40 to +85 c, v dd = av dd = 3.5 to 5.5 v, v ss = av ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit input leakage current i li1 0 v v i v dd for pins other than 10 m a x1 and xt1 i li2 x1 and xt1 20 m a output leakage current i lo 0 v v o v dd 10 m a vdd supply current note i dd1 operation mode f xx = 12.58 mhz 10 20 ma v dd = 4.0 to 5.5 v f xx = 6.29 mhz 5 10 ma v dd = 3.5 to 5.5 v i dd2 halt mode f xx = 12.58 mhz 2.0 4.0 ma v dd = 4.0 to 5.5 v f clk = f xx /8 (stbc = b1h) peripheral operation stops. f xx = 6.29 mhz 1.2 2.4 ma v dd = 3.5 to 5.5 v f clk = f xx /8 (stbc = 31h) peripheral operation stops. i dd3 idle mode f xx = 12.58 mhz 0.6 1.2 ma v dd = 4.0 to 5.5 v f xx = 6.29 mhz 0.3 0.6 ma v dd = 3.5 to 5.5 v pull-up resistor r l v i = 0 v x1 and xt1 15 80 k w note these values are valid when the internal regulator is on (regoff pin = l level). they do not include the av dd and av ref1 currents. m pd784907, 784908 75 data sheet u11680ej2v0ds00 ac characteristics (t a = C40 to +85 c, v dd = av dd = 3.5 to 5.5 v, av ss = v ss = 0 v) (1) read/write operation parameter symbol conditions min. max. unit address setup time (to astb )t sast v dd = 5.0 v (0.5 + a)t C 11 29 ns astb high-level width t wsth v dd = 5.0 v (0.5 + a)t C 17 23 ns address hold time (from astb )t hstla v dd = 5.0 v 0.5t C 19 21 ns address hold time (from rd - )t hra v dd = 5.0 v 0.5t C 14 26 ns delay from address to rd t dar v dd = 5.0 v (1 + a)t C 5 74 ns address float time (from rd )t fra 0ns data input time from address t daid v dd = 5.0 v (2.5 + a + n)t C 37 400 ns data input time from astb t dstid v dd = 5.0 v (2 + n)t C 35 283 ns data input time from rd t drid v dd = 5.0 v (1.5 + n)t C 40 238 ns delay from astb to rd t dstr v dd = 5.0 v 0.5t C 9 31 ns data hold time (from rd - )t hrid 0ns address active time from rd - t dra v dd = 5.0 v 0.5t C 2 38 ns delay from rd - to astb - t drst v dd = 5.0 v 0.5t C 9 31 ns rd low-level width t wrl v dd = 5.0 v (1.5 + n)t C 25 94 ns delay from address to wr t daw v dd = 5.0 v (1 + a)t C 5 74 ns address hold time (from wr - )t hwa v dd = 5.0 v 0.5t C 14 26 ns delay from astb to data output t dstod v dd = 5.0 v 0.5t + 15 55 ns delay from wr to data output t dwod 15 ns delay from astb to wr t dstw v dd = 5.0 v 0.5t C 9 31 ns data setup time (to wr - )t sodwr v dd = 5.0 v (1.5 + n)t C 20 99 ns data hold time (from wr - )t hwod v dd = 5.0 v 0.5t C 14 26 ns delay from wr - to astb - t dwst v dd = 5.0 v 0.5t C 9 31 ns wr low-level width t wwl v dd = 5.0 v (1.5 + n)t C 25 94 ns remark t: t cyk (system clock cycle time) v dd = 5.0 v t = 79 ns (min.) a: 1 during address wait, otherwise, 0 n: number of wait states (n 3 0) m pd784907, 784908 76 data sheet u11680ej2v0ds00 (2) external wait timing parameter symbol conditions min. max. unit wait input time from address t dawt v dd = 5.0 v (2 + a)t C 40 198 ns wait input time from astb t dstwt v dd = 5.0 v 1.5t C 40 79 ns wait hold time from astb t hstwt v dd = 5.0 v (0.5 + n)t + 5 124 ns delay from astb to wait - t dstwth v dd = 5.0 v (1.5 + n)t C 40 238 ns wait input time from rd t drwtl v dd = 5.0 v t C 40 39 ns wait hold time from rd t hrwt v dd = 5.0 v nt + 5 84 ns delay from rd to wait - t drwth v dd = 5.0 v (1 + n)t C 40 198 ns data input time from wait - t dwtid v dd = 5.0 v 0.5t C 5 35 ns delay from wait - to rd - t dwtr v dd = 5.0 v 0.5t 40 ns delay from wait - to wr - t dwtw v dd = 5.0 v 0.5t 40 ns wait input time from wr t dwwtl v dd = 5.0 v t C 40 39 ns wait hold time from wr t hwwt v dd = 5.0 v nt + 5 84 ns delay from wr to wait - t dwwth v dd = 5.0 v (1 + n)t C 40 198 ns remark t: t cyk (system clock cycle time) v dd = 5.0 v t = 79 ns (min.) a: 1 during address wait, otherwise, 0 n: number of wait states (n 3 0) m pd784907, 784908 data sheet u11680ej2v0ds00 77 (3) bus hold timing parameter symbol conditions min. max. unit delay from hldrq - to float t fqhc v dd = 5.0 v (2 + 4 + a + n)t + 50 765 ns delay from hldrq - to hldak - t dhqhhah v dd = 5.0 v (3 + 4 + a + n)t + 30 825 ns delay from float to hldak - t dcfha v dd = 5.0 v t + 30 109 ns delay from hldrq to hldak t dhqlhal v dd = 5.0 v 2t + 40 199 ns delay from hldrq to active t dhac v dd = 5.0 v t C 20 59 ns remark t: t cyk (system clock cycle time) v dd = 5.0 v t = 79 ns (min.) a: 1 during address wait, otherwise, 0 n: number of wait states (n 3 0) (4) refresh timing parameter symbol conditions min. max. unit random read/write cycle time t rc v dd = 5.0 v 3t 238 ns refrq low-level pulse width t wrfql v dd = 5.0 v 1.5t C 25 94 ns delay from astb to refrq t dstrfq v dd = 5.0 v 0.5t C 9 31 ns delay from rd - to refrq t drrfq v dd = 5.0 v 1.5t C 9 110 ns delay from wr - to refrq t dwrfq v dd = 5.0 v 1.5t C 9 110 ns delay from refrq - to astb t drfqst v dd = 5.0 v 0.5t C 9 31 ns refrq high-level pulse width t wrfqh v dd = 5.0 v 1.5t C 25 94 ns remark t: t cyk (system clock cycle time) v dd = 5.0 v t = 79 ns (min.) m pd784907, 784908 78 data sheet u11680ej2v0ds00 serial operation (t a = C40 to +85 c, v dd = 3.5 to 5.5 v, av ss = v ss = 0 v) (1) csi, csi3 parameter symbol conditions min. max. unit serial clock cycle time t cysk0 input f clk = f xx 8/f xx ns (sck0, sck3) except f clk = f xx 4/f clk ns output except f clk = f xx /8 8/f xx ns f clk = f xx /8 16/f xx ns serial clock low-level width t wskl0 input f clk = f xx 4/f xx C 40 ns (sck0, sck3) except f clk = f xx 2/f clk C 40 output except f clk = f xx /8 4/f xx C 40 m s f clk = f xx /8 8/f xx C 40 serial clock high-level width t wskh0 input f clk = f xx 4/f xx C 40 ns (sck0, sck3) except f clk = f xx 2/f clk C 40 output except f clk = f xx /8 4/f xx C 40 m s f clk = f xx /8 8/f xx C 40 si0, si3 setup time t sssk0 80 ns (to sck0, sck3 - ) si0, si3 hold time t hssk0 external clock 1/f clk + 80 ns (from sck0, sck3 - ) internal clock 80 so0, so3 output delay time t dsbsk1 cmos push-pull output external clock 0 1/f clk + 150 ns (from sck0, sck3 ) internal clock 0 150 ns t dsbsk2 open-drain output external clock 0 1/f clk + 400 ns r l = 1 k w internal clock 0 400 ns so0, so3 output hold time t hsbsk when data is transferred 0.5t cysk0 C 40 ns (from sck0, sck3 - ) remarks 1. the values in this table are those when f xx = 12.58 mhz, c l = 100 pf. 2. f clk : system clock frequency (selectable from f xx , f xx /2, f xx /4, and f xx /8 by the standby control register (stbc)) 3. f xx : oscillation frequency (f xx = 12.58 mhz or f xx = 6.29 mhz) m pd784907, 784908 data sheet u11680ej2v0ds00 79 (2) ioe1, ioe2 (t a = C40 to +85 c, v dd = av dd = 3.5 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk1 input v dd = 4.0 to 5.5 v 640 ns (sck1, sck2) 1,280 ns output internal, divided by 8 t ns serial clock low-level width t wskl1 input v dd = 4.0 to 5.5 v 280 ns (sck1, sck2) 600 ns output internal, divided by 8 0.5t C 40 ns serial clock high-level width t wskh1 input v dd = 4.0 to 5.5 v 280 ns (sck1, sck2) 600 ns output internal, divided by 8 0.5t C 40 ns si1, si2 setup time t sssk1 40 ns (to sck1, sck2 - ) si1, si2 hold time t hssk1 40 ns (from sck1, sck2 - ) so1, so2 output delay time t dsosk 050ns (from sck1, sck2 - ) so1, so2 output hold time t hsosk when data is transferred 0.5t cysk1 C 40 ns (from sck1, sck2 - ) remarks 1. the values in this table are those when c l = 100 pf. 2. t: serial clock cycle set by software. the minimum value is 8/f xx . (3) uart, uart2 (t a = C40 to +85 c, v dd = av dd = 3.5 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. max. unit asck clock input cycle time t cyask v dd = 4.5 to 5.5 v 160 ns 320 ns asck clock low-level width t waskl v dd = 4.5 to 5.5 v 65 ns 120 ns asck clock high-level width t waskh v dd = 4.5 to 5.5 v 65 ns 120 ns m pd784907, 784908 80 data sheet u11680ej2v0ds00 clock output operation (t a = C40 to +85 c, v dd = av dd = 3.5 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. max. unit clkout cycle time t cycl nt 79 32,000 ns clkout low-level width t cll v dd = 4.0 to 5.5 v, 0.5t C 10 30 ns 0.5t C 20 20 ns clkout high-levell width t clh v dd = 4.0 to 5.5 v, 0.5t C 10 30 ns 0.5t C 20 20 ns clkout rising time t clr v dd = 4.0 to 5.5 v 10 ns v dd = 3.5 to 4.0 v 0.3 20 ns clkout falling time t clf v dd = 4.0 to 5.5 v 10 ns v dd = 3.5 to 4.0 v 0.3 20 ns remark n: dividing ratio set by software in the cpu (n = 1, 2, 4, 8, and 16) t: t cyk (system clock cycle time) other operations (t a = C40 to +85 c, v dd = av dd = 3.5 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. max. unit nmi low-level width t wnil 10 m s nmi high-level width t wnih 10 m s intp0 low-level width t wit0l 4t cysmp ns intp0 high-level width t wit0h 4t cysmp ns intp1 to intp3 and ci t wit1l 4t cycpu ns low-level width intp1 to intp3 and ci t wit1h 4t cycpu ns high-level width intp4 and intp5 low-level width t wit2l 10 m s intp4 and intp5 high-level width t wit2h 10 m s reset low-level width note t wrsl 10 m s reset high-level width t wrsh 10 m s note when the power is on, secure the oscillation stabilization wait time with the reset low-level width. remark t cysmp : sampling clock set by software t cycpu : cpu operation clock set by software in the cpu m pd784907, 784908 data sheet u11680ej2v0ds00 81 a/d converter characteristics (t a = C40 to +85 c, v dd = av dd = av ref1 = 3.5 to 5.5 v, v ss = av ss = 0 v) parameter symbol conditions min. typ. max. unit resolution 8 bit total error note iead = 00h 0.6 % fr = 1 1.5 % iead = 01h v dd = 4.5 to 5.5 v 1 2.2 % quantization error 1/2 lsb conversion time t conv fr = 1 120/f clk 9.5 480 m s fr = 0 240/f clk 19.1 960 m s sampling time t samp fr = 1 18/f clk 1.4 72 m s fr = 0 36/f clk 2.9 144 m s analog input impedance r an 1,000 m w av ref1 impedance r ref1 310 k w av dd power supply current ai dd1 cs = 1 2.0 5.0 ma ai dd2 cs = 0, stop mode 1.0 20 m a note quantization error is not included. this parameter is indicated as the ratio to the full-scale value. caution to execute the conversion by the a/d converter set port 7, multiplexed with the a/d input lines, to output mode to prevent data from being inverted. remark f clk : system clock frequency (selectable from f xx , f xx /2, f xx /4, and f xx /8 by the standby control register (stbc)) iebus controller characteristics (t a = C40 to +85 c, v dd = av dd = av ref1 = 4.5 to 5.5 v, av ss = v ss = 0 v) parameter symbol conditions min. typ. max. unit iebus standard f s transfer speed: mode 1 6.20 6.29 6.39 mhz frequency note 1 driver delay time (from t dtx c l = 50 pf note 3 1.5 m s tx output to bus line) note 2 receiver delay time (from t drx 0.7 m s bus line to rx input) note 2 transmission delay on t dbus 0.85 m s bus note 2 notes 1. the value conforms to the iebus standard. the iebus controller is operable within the range of the oscillator frequency of oscillator characteristics. 2. iebus system clock: the value is measured when f x = 6.29 mhz. 3. c is the load capacitance of tx output line. m pd784907, 784908 82 data sheet u11680ej2v0ds00 data retention characteristics (t a = C40 to +85 c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 2.5 5.5 v data retention current i dddr stop mode v dddr = 2.5 v, 2 10 m a av ref = 0 v note 1 v dddr = 3.5 to 5.5 v, 10 50 m a av ref = 0 v note 1 v dd rising time t rvd 200 m s v dd falling time t fvd 200 m s v dd hold time t hvd 0 0.6 ms (from stop mode setting) stop clear signal t drel 0ms input time oscillation settling time t wait crystal resonator 30 ms ceramic resonator 5 0.1v dddr ms input low voltage v il specific pins note 2 0v dddr v input high voltage v ih 0.9v dddr v notes 1. valid when input voltages to the pins described in note 2 satisfy v il or v ih in the above table. 2. reset, p12/asck2/sck2, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p32/sck0, p33/so0, p105/sck3, p106/si3, and p107/so3 pins ac timing test points 0.8 v dd or 2.2 v 0.8 v 0.8 v dd or 2.2 v 0.8 v test points v dd ?1 v 0.45 v m pd784907, 784908 data sheet u11680ej2v0ds00 83 timing waveform (1) read operation (2) write operation astb a8 to a19 ad0 to ad7 rd t wsth t sast t dstid t hstla t drst t fra t drid t dar t wrl t dstr t daid t hra t dra t hrid astb a8 to a19 ad0 to ad7 wr t wsth t sast t hstla t dwst t daw t dstw t hwod t dstod t dwod t sodwr t wwl t hwa m pd784907, 784908 84 data sheet u11680ej2v0ds00 hold timing external wait signal input timing (1) read operation (2) write operation hldrq hldak t dhqhhah t fhqc t dcfha t dhac t dhqlhal astb, a8 to a19, ad0 to ad7, rd, wr astb a8 to a19 ad0 to ad7 rd wait t dstwt t hstwth t dstwth t dawt t dwtid t dwtr t drwtl t hrwt t drwth astb a8 to a19 ad0 to ad7 wr wait t dstwt t hstwth t dstwth t dawt t dwtw t dwwtl t hwwt t dwwth m pd784907, 784908 data sheet u11680ej2v0ds00 85 refresh timing waveform (1) random read/write cycle (2) when refresh memory is accessed for a read and write at the same time (3) refresh after a read (4) refresh after a write astb wr rd t rc t rc t rc t rc t rc t wrfql astb rd, wr refrq t dstrfq t drfqst t wrfqh astb rd refrq t drfqst t drrfq t wrfql astb wr refrq t drfqst t dwrfq t wrfql m pd784907, 784908 86 data sheet u11680ej2v0ds00 serial operation (csi, csi3) serial operation (ioe1, ioe2) serial operation (uart, uart2) clock output timing sck0, sck3 si0, si3 so0, so3 output data input data t sssk0 t hssk0 t dsbsk1 t wskl0 t wskh0 t hsbsk1 t cysk0 sck1, sck2 si1, si2 so1, so2 output data input data t sssk1 t hssk1 t dsosk t hsosk t wskl1 t wskh1 t cysk1 asck, asck2 t waskh t waskl t cyask clkout t clh t cll t cycl t clf t clr m pd784907, 784908 data sheet u11680ej2v0ds00 87 interrupt request input timing reset input timing nmi intp0 ci, intp1 to intp3 intp4, intp5 t wnih t wnil t wit0h t wit0l t wit1h t wit1l t wit2h t wit2l reset t wrsh t wrsl m pd784907, 784908 88 data sheet u11680ej2v0ds00 external clock timing data retention characteristics x1 t wxh t wxl t cyx t xf t xr v dd reset nmi (clearing by falling edge) nmi (clearing by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait m pd784907, 784908 data sheet u11680ej2v0ds00 89 remark the shape and material of the es version are the same as those of the corresponding mass-produced product. 16. package drawing 100 pin plastic qfp (14 20) item millimeters inches note each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. p100gf-65-3ba1-3 b 20.0 0.2 0.795 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.6 0.4 0.693 0.016 f 0.8 0.031 g 0.6 0.024 h 0.30 0.10 0.012 i 0.15 0.006 j 0.65 (t.p.) 0.026 (t.p.) k 1.8 0.2 0.071 +0.008 ?.009 l 0.8 0.2 0.031 n 0.10 0.004 q 0.1 0.1 0.004 0.004 s 3.0 max. 0.119 max. detail of lead end r q j k m l n p g f h i m p 2.7 0.1 0.106 +0.005 ?.004 80 81 50 100 1 31 30 51 b a cd s a 23.6 0.4 0.929 0.016 m 0.15 0.006 +0.10 ?.05 r5 5 5 5 +0.004 ?.005 +0.009 ?.008 +0.004 ?.003 m pd784907, 784908 90 data sheet u11680ej2v0ds00 soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c ir35-00-3 time: 30 seconds max. (210 c or higher) count: three times or less vps package peak temperature: 215 c vp15-00-3 time: 40 seconds or max. (200 c or higher) count: three times or less wave soldering solder bath temperature: 260 c max. ws60-00-1 time: 10 seconds max. count : 1 preheating temperature: 120 c max. (package surface temperature) partial heating method pin temperature: 300 c time: 3 seconds max. (per pin row) 17. recommended soldering conditions the m pd784908 should be soldered under the following recommended conditions. for details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended below, contact your nec sales represen- tative. table 17-1. soldering conditions for surface mount type m pd784907gf- -3ba: 100-pin plastic qfp (14 20 mm) m pd784908gf- -3ba: 100-pin plastic qfp (14 20 mm) caution do not use different soldering methods together (except for partial heating). m pd784907, 784908 data sheet u11680ej2v0ds00 91 appendix a development tools the following development tools are available for system development using the m pd784908. also refer to (5) cautions on using development tools . (1) language processing software ra78k4 assembler package common to 78k/iv series cc78k4 c compiler package common to 78k/iv series df784908 device file for m pd784908 subseries cc78k4-l c compiler library source file common to 78k/iv series (2) prom write tools pg-1500 prom programmer pa-78p4908gf programmer adapter, connects to pg-1500 pg-1500 controller control program for pg-1500 (3) debugging tools ? when using the in-circuit emulator ie-78k4-ns ie-78k4-ns in-circuit emulator common to 78k/iv series ie-70000-mc-ps-b power supply unit for ie-78k4-ns ie-70000-98-if-c interface adapter when a pc-9800 series computer (except notebook type) is used as the host machine (c bus supported) ie-70000-cd-if-a pc card and interface cable when a notebook type is used as the host machine (pcmcia socket supported) ie-70000-pc-if-c interface adapter when an ibm pc/at tm or compatible is used as the host machine (isa bus supported) ie-70000-pci-if adapter when a pc that incorporates a pci bus is used as the host machine ie-784908-ns-em1 emulation board to emulate m pd784908 subseries np-100gf note emulation probe for 100-pin plastic qfp (gf-3ba type) ev-9200gf-100 socket to be mounted on target system board made for 100-pin plastic qfp (gf-3ba type). used in lcc mode. id78k4-ns integrated debugger for ie-78k4-ns sm78k4 system simulator common to 78k/iv series df784908 device file for m pd784908 subseries note under development m pd784907, 784908 92 data sheet u11680ej2v0ds00 ? when using the in-circuit emulator ie-784000-r ie-784000-r in-circuit emulator common to 78k/iv series ie-70000-98-if-c interface adapter when a pc-9800 series computer (except notebook type) is used as the host machine (c bus supported) ie-70000-pc-if-c interface adapter when an ibm pc/at or compatible is used as the host machine (isa bus supported) ie-70000-pci-if adapter when a pc that incorporates a pci bus is used as the host machine ie-78000-r-sv3 interface adapter and cable when the ews is used as the host machine ie-784908-ns-em1 emulation board to emulate m pd784908 subseries ie-784908-r-em1 ie-784000-r-em emulation board common to 78k/iv series ie-78k4-r-ex2 conversion board for emulation probes required to use the ie-784908-ns- em1 on the ie-784000-r. the board is not needed when the conventional product ie-784908-r-em1 is used. ep-78064-gf-r emulation probe for 100-pin plastic qfp (gf-3ba type) ev-9200gf-100 socket to be mounted on target system board made for 100-pin plastic qfp (gf-3ba type) id78k4 integrated debugger for ie-784000-r sm78k4 system simulator common to 78k/iv series df784908 device file for m pd784908 subseries (4) real-time os rx78k/iv real-time os for 78k/iv series mx78k4 os for 78k/iv series m pd784907, 784908 data sheet u11680ej2v0ds00 93 (5) cautions on using development tools ? the id78k4-ns, id78k4, and sm78k4 are used in combination with the df784908. ? the cc78k4 and rx78k/iv are used in combination with the ra78k4 and df784908. ? the np-100gf is a product made by naito densei machidaseisakusho co., ltd. (+81-44-822-3813). contact an nec distributor regarding the purchase of these products. ? the host machines and oss suitable for each software are as follows. host machine pc ews [os] pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles sparcstation tm [sunos tm , solaris tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k4 ? note ? cc78k4 ? note ? pg-1500 controller ? note id78k4-ns ? id78k4 ?? sm78k4 ? rx78k/iv ? note ? mx78k4 ? note ? note dos-based software m pd784907, 784908 94 data sheet u11680ej2v0ds00 appendix b related documents documents related to devices document name document no. japanese english m pd784907, 784908 data sheet u11680j this manual m pd78p4908 data sheet u11681j u11681e m pd784908 subseries user's manual hardware u11787j u11787e m pd784908 subseries special function register table u11589j 78k/iv series user's manual instructions u10905j u10905e 78k/iv series instruction table u10594j 78k/iv series instruction set u10595j 78k/iv series application note software basics u10095j u10095e documents related to development tools (user's manual) document name document no. japanese english ra78k4 assembler package language u11162j u11162e operation u11334j u11334e ra78k4 structured assembler preprocessor u11743j u11743e cc78k4 c compiler language u11571j u11571e operation u11572j u11572e pg-1500 prom programmer u11940j u11940e pg-1500 controller pc-9800 series (ms-dos tm ) based eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos tm ) based eeu-5008 u10540e ie-78k4-ns u13356j u13356e ie-784000-r u12903j u12903e ie-784908-r-em1 u11876j ie-784908-ns-em1 u13743j under preparation ep-78064 eeu-934 eeu-1469 sm78k4 system simulator windows based reference u10093j u10093e sm78k series system simulator external part user open u10092j u10092e interface specifications id78k4-ns integrated debugger pc based reference u12796j u12796e id78k4 integrated debugger windows based reference u10440j u10440e id78k4 integrated debugger hp-ux, sunos, news-os based reference u11960j u11960e caution the above documents may be revised without notice. use the latest versions when you design application systems. m pd784907, 784908 data sheet u11680ej2v0ds00 95 documents related to embedded software (user's manual) document name document no. japanese english 78k/iv series real-time os fundamental u10603j u10603e installation u10604j u10604e debugger u10364j 78k/iv series os mx78k4 fundamental u11779j other documents document name document no. japanese english nec ic package manual (cd-rom) c13388e semiconductor device mounting technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) c11892j c11892e guide to quality assurance for semiconductor devices mei-1202 guide to microcontroller-related products by third parties u11416j caution the above documents may be revised without notice. use the latest versions when you design application systems. m pd784907, 784908 96 data sheet u11680ej2v0ds00 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. m pd784907, 784908 data sheet u11680ej2v0ds00 97 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j98. 11 m pd784907, 784908 data sheet u11680ej2v0ds00 the related documents in this publication may include preliminary version. however, what preliminary versions are not marked as such. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5 fip, iebus, and eeprom are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of international business machines corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. solaris and sunos are trademarks of sun microsystems, inc. news and news-os are trademarks of sony corporation. |
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